Browse Source

For all source files update integer types to the new gI8 etc type names

inmarket 2 years ago
parent
commit
7c5a6c928f
100 changed files with 1126 additions and 1124 deletions
  1. 1 1
      boards/addons/gdisp/board_ED060SC4_example.h
  2. 4 4
      boards/addons/gdisp/board_HX8347D_stm32f4discovery.h
  3. 5 5
      boards/addons/gdisp/board_ILI9320_olimex_pic32mx_lcd.h
  4. 6 6
      boards/addons/gdisp/board_ILI9325_hy_stm32_100p.h
  5. 6 6
      boards/addons/gdisp/board_ILI9341_spi.h
  6. 5 5
      boards/addons/gdisp/board_ILI9481_firebullstm32f103.h
  7. 7 7
      boards/addons/gdisp/board_ILI9488_stm32f4cube_hal.h
  8. 6 6
      boards/addons/gdisp/board_S6D1121_olimex_e407.h
  9. 8 8
      boards/addons/gdisp/board_SPFD54124B_stm32f3.h
  10. 6 6
      boards/addons/gdisp/board_SSD1289_stm32f4discovery.h
  11. 3 3
      boards/addons/gdisp/board_SSD1306_chibios_16.1.3_stm32f4.h
  12. 5 5
      boards/addons/gdisp/board_SSD1306_i2c.h
  13. 4 4
      boards/addons/gdisp/board_SSD1963_fsmc.h
  14. 2 2
      boards/addons/gdisp/board_SSD1963_gpio.h
  15. 3 3
      boards/addons/gdisp/board_UC8173_nordic_nrf52_sdk11.h
  16. 4 4
      boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_olimex_stm32_e407.h
  17. 4 4
      boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_st_stm32f4_discovery.h
  18. 4 4
      boards/addons/ginput/touch/ADS7843/stm32f4cube_hal.h
  19. 2 2
      boards/base/Altera-MAX10-Neek/board_alteraframereader.h
  20. 7 7
      boards/base/Altera-MAX10-Neek/gmouse_lld_FT5316_board.h
  21. 4 4
      boards/base/ArduinoTinyScreen/gfx/board_SSD1331.cpp
  22. 2 2
      boards/base/ArduinoTinyScreen/gfx/board_SSD1331.h
  23. 6 6
      boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h
  24. 7 7
      boards/base/Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h
  25. 4 4
      boards/base/FireBull-STM32F103-FB/board_SSD1289.h
  26. 4 4
      boards/base/FireBull-STM32F103-FB/gmouse_lld_ADS7843_board.h
  27. 6 6
      boards/base/HY-MiniSTM32V/board_SSD1289.h
  28. 4 4
      boards/base/HY-MiniSTM32V/gmouse_lld_ADS7843_board.h
  29. 2 2
      boards/base/Linux-Framebuffer/board_framebuffer.h
  30. 5 5
      boards/base/Marlin/board_RA8875.h
  31. 7 7
      boards/base/Marlin/gmouse_lld_FT5x06_board.h
  32. 13 13
      boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/flash_memory.c
  33. 5 5
      boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/flash_memory.h
  34. 4 4
      boards/base/Mikromedia-Plus-STM32-M4/board_SSD1963.h
  35. 7 7
      boards/base/Mikromedia-Plus-STM32-M4/gmouse_lld_STMPE610_board.h
  36. 13 13
      boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/flash_memory.c
  37. 5 5
      boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/flash_memory.h
  38. 7 7
      boards/base/Mikromedia-STM32-M4-ILI9341/board_ILI9341.h
  39. 3 3
      boards/base/Olimex-SAM7EX256-GE12/board_Nokia6610GE12.h
  40. 3 3
      boards/base/Olimex-SAM7EX256-GE8/board_Nokia6610GE8.h
  41. 4 4
      boards/base/Olimex-SAM7EX256-GE8/board_SSD1306_i2c.h
  42. 5 5
      boards/base/Olimex-SAM7EX256-GE8/board_SSD1306_spi.h
  43. 5 5
      boards/base/Olimex-SAM7EX256-GE8/board_SSD1331.h
  44. 5 5
      boards/base/Olimex-SAM7EX256-GE8/board_TLS8204.h
  45. 3 3
      boards/base/Olimex-SAM7EX256-GE8/gaudio_play_board.h
  46. 1 1
      boards/base/Olimex-SAM7EX256-GE8/gaudio_record_board.h
  47. 6 6
      boards/base/Olimex-STM32-LCD/board_ILI9320.h
  48. 1 1
      boards/base/Olimex-STM32-LCD/gmouse_lld_MCU_board.h
  49. 5 5
      boards/base/RaspberryPi/FreeRTOS/mmio.h
  50. 4 4
      boards/base/RaspberryPi/FreeRTOS/uart.c
  51. 2 2
      boards/base/RaspberryPi/FreeRTOS/uart.h
  52. 12 12
      boards/base/RaspberryPi/board_framebuffer.h
  53. 7 7
      boards/base/STM32F429i-Discovery/chibios/board_STM32LTDC.h
  54. 7 7
      boards/base/STM32F429i-Discovery/chibios/gmouse_lld_STMPE811_board.h
  55. 8 8
      boards/base/STM32F429i-Discovery/chibios/stm32f429i_discovery_sdram.c
  56. 14 14
      boards/base/STM32F429i-Discovery/chibios/stm32f429i_discovery_sdram.h
  57. 68 68
      boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c
  58. 171 171
      boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.h
  59. 1 1
      boards/base/STM32F439i-Eval/CubeHal/board_STM32LTDC.h
  60. 3 3
      boards/base/STM32F439i-Eval/CubeHal/gmouse_lld_EXC7200_board.h
  61. 14 14
      boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.c
  62. 22 22
      boards/base/STM32F439i-Eval/CubeHal/stm324x9i_eval_sdram.h
  63. 13 13
      boards/base/STM32F439i-Eval/CubeHal/stm32f439i_raw32_system.c
  64. 4 4
      boards/base/STM32F469i-Discovery/CubeHAL/board_STM32LTDC.h
  65. 8 8
      boards/base/STM32F469i-Discovery/CubeHAL/gmouse_lld_FT6x06_board.h
  66. 184 184
      boards/base/STM32F469i-Discovery/otm8009a.c
  67. 17 17
      boards/base/STM32F469i-Discovery/otm8009a.h
  68. 16 16
      boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.c
  69. 25 25
      boards/base/STM32F469i-Discovery/stm32f469i_discovery_sdram.h
  70. 12 12
      boards/base/STM32F469i-Discovery/stm32f469i_raw32_system.c
  71. 1 1
      boards/base/STM32F746-Discovery/board_STM32LTDC.h
  72. 28 28
      boards/base/STM32F746-Discovery/example_chibios3/stm32f7xx_hal_conf.h
  73. 38 38
      boards/base/STM32F746-Discovery/example_raw32/stm32f7xx_hal_conf.h
  74. 5 5
      boards/base/STM32F746-Discovery/gmouse_lld_FT5336_board.h
  75. 47 47
      boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.c
  76. 2 2
      boards/base/STM32F746-Discovery/stm32f746g_discovery_sdram.h
  77. 11 11
      boards/base/STM32F746-Discovery/stm32f746g_raw32_system.c
  78. 15 15
      boards/base/STM32F746-Discovery/stm32f7_i2c.c
  79. 6 6
      boards/base/STM32F746-Discovery/stm32f7_i2c.h
  80. 3 3
      boards/base/eCos-Synthetic-Framebuffer/board_framebuffer.h
  81. 3 1
      changelog.txt
  82. 25 25
      demos/3rdparty/bubbles/main.c
  83. 1 1
      demos/3rdparty/notepad-2/main.c
  84. 1 1
      demos/3rdparty/notepad-2/notepadApp.c
  85. 9 9
      demos/3rdparty/notepad-2/notepadCore.c
  86. 4 4
      demos/3rdparty/notepad-2/notepadCore.h
  87. 1 1
      demos/applications/combo/mandelbrot.c
  88. 1 1
      demos/applications/mandelbrot/main.c
  89. 1 1
      demos/applications/notepad/main.c
  90. 1 1
      demos/benchmarks/main.c
  91. 27 27
      demos/games/justget10/jg10.c
  92. 14 14
      demos/games/minesweeper/mines.c
  93. 4 4
      demos/games/minesweeper/resources/romfs/userfonts.h
  94. 6 6
      demos/games/tetris/Example_Makefiles/stm32f4/board_SSD1289.h
  95. 4 4
      demos/games/tetris/Example_Makefiles/stm32f4/ginput_lld_mouse_board.h
  96. 4 4
      demos/games/tetris/Example_Makefiles/stm32f4/gmouse_lld_ADS7843_board.h
  97. 4 4
      demos/games/tetris/Example_Makefiles/stm32f4/gmouse_lld_ADS7843_board.h.old
  98. 6 6
      demos/games/tetris/Example_Makefiles/stm32f4_chibios_3.x/board_SSD1289.h
  99. 4 4
      demos/games/tetris/Example_Makefiles/stm32f4_chibios_3.x/ginput_lld_mouse_board.h
  100. 0 0
      demos/games/tetris/Example_Makefiles/stm32f4_chibios_3.x/gmouse_lld_ADS7843_board.h

+ 1 - 1
boards/addons/gdisp/board_ED060SC4_example.h

@@ -119,7 +119,7 @@ static GFXINLINE void setpin_sph(GDisplay *g, gBool on) {
119 119
 }
120 120
 
121 121
 /* Set the state of the D0-D7 (source driver Data) pins. */
122
-static GFXINLINE void setpins_data(GDisplay *g, uint8_t value) {
122
+static GFXINLINE void setpins_data(GDisplay *g, gU8 value) {
123 123
 	(void) g;
124 124
 	palWriteGroup(GPIOB, 0xFF, GPIOB_EINK_D0, value);
125 125
 }

+ 4 - 4
boards/addons/gdisp/board_HX8347D_stm32f4discovery.h

@@ -112,7 +112,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
112 112
 	}
113 113
 }
114 114
 
115
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
115
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
116 116
 	(void) g;
117 117
 	pwmEnableChannel(&PWMD4, 1, percent);
118 118
 }
@@ -140,7 +140,7 @@ static GFXINLINE void busmode8(GDisplay *g) {
140 140
 	spiStart(&SPID1, &spi1cfg_8bit);
141 141
 }
142 142
 
143
-static GFXINLINE void write_index(GDisplay *g, uint8_t index) {
143
+static GFXINLINE void write_index(GDisplay *g, gU8 index) {
144 144
 	(void) g;
145 145
     CLR_DATA;
146 146
     SPI1->DR = index;
@@ -148,13 +148,13 @@ static GFXINLINE void write_index(GDisplay *g, uint8_t index) {
148 148
     SET_DATA;
149 149
 }
150 150
 
151
-static GFXINLINE void write_data(GDisplay *g, uint8_t data) {
151
+static GFXINLINE void write_data(GDisplay *g, gU8 data) {
152 152
 	(void) g;
153 153
     SPI1->DR = data;
154 154
     while(((SPI1->SR & SPI_SR_TXE) == 0) || ((SPI1->SR & SPI_SR_BSY) != 0));
155 155
 }
156 156
 
157
-static GFXINLINE void write_ram16(GDisplay *g, uint16_t data) {
157
+static GFXINLINE void write_ram16(GDisplay *g, gU16 data) {
158 158
 	(void) g;
159 159
     SPI1->DR      = data;
160 160
     while((SPI1->SR & SPI_SR_TXE) == 0);

+ 5 - 5
boards/addons/gdisp/board_ILI9320_olimex_pic32mx_lcd.h

@@ -76,7 +76,7 @@ static noinline void setpin_reset(GDisplay *g, gBool state) {
76 76
 		palSetPad(IOPORTA, 7);
77 77
 }
78 78
 
79
-static void set_backlight(GDisplay *g, uint8_t percent) {
79
+static void set_backlight(GDisplay *g, gU8 percent) {
80 80
 	(void) g;
81 81
 	if (percentage)
82 82
 		palClearPad(IOPORTD, 3);
@@ -92,8 +92,8 @@ static GFXINLINE void release_bus(GDisplay *g) {
92 92
 	(void) g;
93 93
 }
94 94
 
95
-static noinline void write_index(GDisplay *g, uint16_t index) {
96
-	volatile uint16_t dummy;
95
+static noinline void write_index(GDisplay *g, gU16 index) {
96
+	volatile gU16 dummy;
97 97
 	(void) g;
98 98
 
99 99
 	PmpWaitBusy();
@@ -106,7 +106,7 @@ static noinline void write_index(GDisplay *g, uint16_t index) {
106 106
 	(void)dummy;
107 107
 }
108 108
 
109
-static noinline void write_data(GDisplay *g, uint16_t data) {
109
+static noinline void write_data(GDisplay *g, gU16 data) {
110 110
 	(void) g;
111 111
 	PMDIN = data;
112 112
 	PmpWaitBusy();
@@ -120,7 +120,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
120 120
 	(void) g;
121 121
 }
122 122
 
123
-static noinline uint16_t read_data(GDisplay *g) {
123
+static noinline gU16 read_data(GDisplay *g) {
124 124
 	(void) g;
125 125
 	PmpWaitBusy();
126 126
 	return PMDIN;

+ 6 - 6
boards/addons/gdisp/board_ILI9325_hy_stm32_100p.h

@@ -31,8 +31,8 @@
31 31
 
32 32
 // For a multiple display configuration we would put all this in a structure and then
33 33
 //	set g->board to that structure.
34
-#define GDISP_REG              (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
35
-#define GDISP_RAM              (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
34
+#define GDISP_REG              (*((volatile gU16 *) 0x60000000)) /* RS = 0 */
35
+#define GDISP_RAM              (*((volatile gU16 *) 0x60020000)) /* RS = 1 */
36 36
 
37 37
 static GFXINLINE void init_board(GDisplay *g) {
38 38
 
@@ -76,7 +76,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
76 76
 		palSetPad(GPIOE, GPIOE_TFT_RST);
77 77
 }
78 78
 
79
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
79
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
80 80
 	(void) g;
81 81
 	(void)percent;
82 82
 }
@@ -89,12 +89,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
89 89
 	(void) g;
90 90
 }
91 91
 
92
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
92
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
93 93
 	(void) g;
94 94
 	GDISP_REG = index;
95 95
 }
96 96
 
97
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
97
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
98 98
 	(void) g;
99 99
 	GDISP_RAM = data;
100 100
 }
@@ -107,7 +107,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
107 107
 	(void) g;
108 108
 }
109 109
 
110
-static GFXINLINE uint16_t read_data(GDisplay *g) {
110
+static GFXINLINE gU16 read_data(GDisplay *g) {
111 111
 	(void) g;
112 112
 	return GDISP_RAM;
113 113
 }

+ 6 - 6
boards/addons/gdisp/board_ILI9341_spi.h

@@ -43,7 +43,7 @@ static const SPIConfig spi2cfg = {
43 43
   (SPI_CR1_MSTR | SPI_CR1_SPE | SPI_CR1_SSM | SPI_CR1_SSI)
44 44
 };
45 45
 
46
-static void send_data(uint16_t data);
46
+static void send_data(gU16 data);
47 47
 
48 48
 /**
49 49
  * @brief   Initialise the board for the display.
@@ -105,7 +105,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
105 105
  * 
106 106
  * @notapi
107 107
  */
108
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
108
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
109 109
 	(void) g;
110 110
 	(void) percent;
111 111
 }
@@ -139,7 +139,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
139 139
  * 
140 140
  * @notapi
141 141
  */
142
-static GFXINLINE void send_data(uint16_t data) {
142
+static GFXINLINE void send_data(gU16 data) {
143 143
 // http://forum.easyelectronics.ru/viewtopic.php?p=262122#p262122
144 144
   while (!(SPI2->SR & SPI_SR_TXE)); // ïðè âõîäå íà îòïðàâêó ïðîâåðÿåì - à ïóñòîé ëè SPI_DR
145 145
   SPI2->DR = data; // çàãðóçèëè â SPI_DR êîä êîìàíäû
@@ -154,7 +154,7 @@ static GFXINLINE void send_data(uint16_t data) {
154 154
  *
155 155
  * @notapi
156 156
  */
157
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
157
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
158 158
 	(void) g;
159 159
 
160 160
   while (SPI2->SR & SPI_SR_BSY);
@@ -177,7 +177,7 @@ static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
177 177
  * 
178 178
  * @notapi
179 179
  */
180
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
180
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
181 181
 	(void) g;
182 182
 
183 183
   send_data(data);
@@ -213,7 +213,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
213 213
  *
214 214
  * @notapi
215 215
  */
216
-static GFXINLINE uint16_t read_data(GDisplay *g) {
216
+static GFXINLINE gU16 read_data(GDisplay *g) {
217 217
 	(void) g;
218 218
 	return 0;
219 219
 }

+ 5 - 5
boards/addons/gdisp/board_ILI9481_firebullstm32f103.h

@@ -58,7 +58,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
58 58
 	(void) state;
59 59
 }
60 60
 
61
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
61
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
62 62
 	(void) g;
63 63
 	(void) percent;
64 64
 }
@@ -71,13 +71,13 @@ static GFXINLINE void release_bus(GDisplay *g) {
71 71
 	(void) g;
72 72
 }
73 73
 
74
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
74
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
75 75
 	(void) g;
76 76
 	palWritePort(GPIOE, index);
77 77
 	CLR_RS; CLR_WR; SET_WR; SET_RS;
78 78
 }
79 79
 
80
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
80
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
81 81
 	(void) g;
82 82
 	palWritePort(GPIOE, data);
83 83
 	CLR_WR; SET_WR;
@@ -95,8 +95,8 @@ static GFXINLINE void setwritemode(GDisplay *g) {
95 95
 	palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
96 96
 }
97 97
 
98
-static GFXINLINE uint16_t read_data(GDisplay *g) {
99
-	uint16_t	value;
98
+static GFXINLINE gU16 read_data(GDisplay *g) {
99
+	gU16	value;
100 100
 	(void) g;
101 101
 	
102 102
 	CLR_RD;

+ 7 - 7
boards/addons/gdisp/board_ILI9488_stm32f4cube_hal.h

@@ -10,8 +10,8 @@
10 10
 
11 11
 #include "stm32f4xx_hal.h"
12 12
 
13
-#define GDISP_REG              (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
14
-#define GDISP_RAM              (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
13
+#define GDISP_REG              (*((volatile gU16 *) 0x60000000)) /* RS = 0 */
14
+#define GDISP_RAM              (*((volatile gU16 *) 0x60020000)) /* RS = 1 */
15 15
 
16 16
 static GFXINLINE void init_board(GDisplay *g)
17 17
 {
@@ -108,7 +108,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state)
108 108
   }
109 109
 }
110 110
 
111
-static GFXINLINE void set_backlight(GDisplay* g, uint8_t percent)
111
+static GFXINLINE void set_backlight(GDisplay* g, gU8 percent)
112 112
 {
113 113
 	(void) g;
114 114
 
@@ -129,14 +129,14 @@ static GFXINLINE void release_bus(GDisplay* g)
129 129
 	(void) g;
130 130
 }
131 131
 
132
-static GFXINLINE void write_index(GDisplay* g, uint16_t index)
132
+static GFXINLINE void write_index(GDisplay* g, gU16 index)
133 133
 {
134 134
 	(void) g;
135 135
 
136 136
   GDISP_REG = index;
137 137
 }
138 138
 
139
-static GFXINLINE void write_data(GDisplay* g, uint16_t data)
139
+static GFXINLINE void write_data(GDisplay* g, gU16 data)
140 140
 {
141 141
 	(void) g;
142 142
 
@@ -153,11 +153,11 @@ static GFXINLINE void setwritemode(GDisplay* g)
153 153
 	(void) g;
154 154
 }
155 155
 
156
-static GFXINLINE uint16_t read_data(GDisplay* g)
156
+static GFXINLINE gU16 read_data(GDisplay* g)
157 157
 {
158 158
 	(void) g;
159 159
 
160
-	return (uint16_t)GDISP_RAM;
160
+	return (gU16)GDISP_RAM;
161 161
 }
162 162
 
163 163
 #endif /* _GDISP_LLD_BOARD_H */

+ 6 - 6
boards/addons/gdisp/board_S6D1121_olimex_e407.h

@@ -18,8 +18,8 @@
18 18
 
19 19
 // For a multiple display configuration we would put all this in a structure and then
20 20
 //	set g->board to that structure.
21
-#define GDISP_REG              (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
22
-#define GDISP_RAM              (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
21
+#define GDISP_REG              (*((volatile gU16 *) 0x60000000)) /* RS = 0 */
22
+#define GDISP_RAM              (*((volatile gU16 *) 0x60020000)) /* RS = 1 */
23 23
 
24 24
 static GFXINLINE void init_board(GDisplay *g) {
25 25
 
@@ -55,7 +55,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
55 55
 	(void) state;
56 56
 }
57 57
 
58
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
58
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
59 59
 	(void) g;
60 60
 	(void) percent;
61 61
 }
@@ -68,12 +68,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
68 68
 	(void) g;
69 69
 }
70 70
 
71
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
71
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
72 72
 	(void) g;
73 73
 	GDISP_REG = index;
74 74
 }
75 75
 
76
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
76
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
77 77
 	(void) g;
78 78
 	GDISP_RAM = data;
79 79
 }
@@ -86,7 +86,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
86 86
 	(void) g;
87 87
 }
88 88
 
89
-static GFXINLINE uint16_t read_data(GDisplay *g) {
89
+static GFXINLINE gU16 read_data(GDisplay *g) {
90 90
 	(void) g;
91 91
 	return GDISP_RAM;
92 92
 }

+ 8 - 8
boards/addons/gdisp/board_SPFD54124B_stm32f3.h

@@ -37,7 +37,7 @@
37 37
 #if USE_HARD_SPI
38 38
 
39 39
 #if GFX_USE_OS_CHIBIOS
40
-static int32_t thdPriority = 0;
40
+static gI32 thdPriority = 0;
41 41
 #endif
42 42
 
43 43
 /*
@@ -58,9 +58,9 @@ static GFXINLINE void soft_spi_sck(void){
58 58
   palClearPad(SPFD54124B_SPI_PORT, SPFD54124B_SPI_SCK);
59 59
 }
60 60
 
61
-static GFXINLINE void soft_spi_write_9bit(uint16_t data){
61
+static GFXINLINE void soft_spi_write_9bit(gU16 data){
62 62
 
63
-  uint8_t i;
63
+  gU8 i;
64 64
 
65 65
   // activate lcd by low on CS pin
66 66
   palClearPad(SPFD54124B_SPI_PORT, SPFD54124B_SPI_NSS);
@@ -131,7 +131,7 @@ static GFXINLINE void acquire_bus(GDisplay *g) {
131 131
   (void) g;
132 132
 #if USE_HARD_SPI
133 133
 #if GFX_USE_OS_CHIBIOS
134
-  thdPriority = (int32_t)chThdGetPriority();
134
+  thdPriority = (gI32)chThdGetPriority();
135 135
   chThdSetPriority(HIGHPRIO);
136 136
 #endif
137 137
   spiAcquireBus(&SPFD54124B_SPID);
@@ -148,10 +148,10 @@ static GFXINLINE void release_bus(GDisplay *g) {
148 148
 #endif
149 149
 }
150 150
 
151
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
151
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
152 152
   (void) g;
153 153
 
154
-  uint16_t b;
154
+  gU16 b;
155 155
 
156 156
 #if USE_HARD_SPI
157 157
 
@@ -176,7 +176,7 @@ static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
176 176
 
177 177
 }
178 178
 
179
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
179
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
180 180
   (void)    g;
181 181
 
182 182
 #if USE_HARD_SPI
@@ -195,7 +195,7 @@ static GFXINLINE void post_init_board(GDisplay *g) {
195 195
   (void) g;
196 196
 }
197 197
 
198
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
198
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
199 199
   (void) g;
200 200
   (void) percent;
201 201
 }

+ 6 - 6
boards/addons/gdisp/board_SSD1289_stm32f4discovery.h

@@ -18,8 +18,8 @@
18 18
 
19 19
 // For a multiple display configuration we would put all this in a structure and then
20 20
 //	set g->board to that structure.
21
-#define GDISP_REG              ((volatile uint16_t *) 0x60000000)[0] /* RS = 0 */
22
-#define GDISP_RAM              ((volatile uint16_t *) 0x60020000)[0] /* RS = 1 */
21
+#define GDISP_REG              ((volatile gU16 *) 0x60000000)[0] /* RS = 0 */
22
+#define GDISP_RAM              ((volatile gU16 *) 0x60020000)[0] /* RS = 1 */
23 23
 #define GDISP_DMA_STREAM		STM32_DMA2_STREAM6
24 24
 #define FSMC_BANK				0
25 25
 
@@ -114,7 +114,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
114 114
 	(void) state;
115 115
 }
116 116
 
117
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
117
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
118 118
 	(void) g;
119 119
     pwmEnableChannel(&PWMD3, 2, percent);
120 120
 }
@@ -127,12 +127,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
127 127
 	(void) g;
128 128
 }
129 129
 
130
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
130
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
131 131
 	(void) g;
132 132
 	GDISP_REG = index;
133 133
 }
134 134
 
135
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
135
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
136 136
 	(void) g;
137 137
 	GDISP_RAM = data;
138 138
 }
@@ -147,7 +147,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
147 147
 	FSMC_Bank1->BTCR[FSMC_BANK+1] = FSMC_BTR1_ADDSET_0 | FSMC_BTR1_DATAST_2 | FSMC_BTR1_BUSTURN_0;		/* FSMC timing */
148 148
 }
149 149
 
150
-static GFXINLINE uint16_t read_data(GDisplay *g) {
150
+static GFXINLINE gU16 read_data(GDisplay *g) {
151 151
 	(void) g;
152 152
 	return GDISP_RAM;
153 153
 }

+ 3 - 3
boards/addons/gdisp/board_SSD1306_chibios_16.1.3_stm32f4.h

@@ -72,17 +72,17 @@ static GFXINLINE void release_bus(GDisplay* g)
72 72
 	spiReleaseBus(SPI_DRIVER);
73 73
 }
74 74
 
75
-static GFXINLINE void write_cmd(GDisplay* g, uint8_t cmd)
75
+static GFXINLINE void write_cmd(GDisplay* g, gU8 cmd)
76 76
 {
77 77
 	(void)g;
78 78
 
79
-	static uint8_t buf;
79
+	static gU8 buf;
80 80
 	palClearPad(DC_PORT, DC_PAD);
81 81
 	buf = cmd;
82 82
 	spiSend(SPI_DRIVER, 1, &buf);
83 83
 }
84 84
 
85
-static GFXINLINE void write_data(GDisplay* g, uint8_t* data, uint16_t length)
85
+static GFXINLINE void write_data(GDisplay* g, gU8* data, gU16 length)
86 86
 {
87 87
 	(void)g;
88 88
 

+ 5 - 5
boards/addons/gdisp/board_SSD1306_i2c.h

@@ -46,7 +46,7 @@
46 46
 static I2CConfig i2cconfig;
47 47
 
48 48
 #if GFX_USE_OS_CHIBIOS
49
-	static int32_t thdPriority = 0;
49
+	static gI32 thdPriority = 0;
50 50
 #endif
51 51
 
52 52
 static GFXINLINE void init_board(GDisplay *g) {
@@ -93,7 +93,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
93 93
 static GFXINLINE void acquire_bus(GDisplay *g) {
94 94
 	(void) g;
95 95
 	#if GFX_USE_OS_CHIBIOS
96
-		thdPriority = (int32_t)chThdGetPriority();
96
+		thdPriority = (gI32)chThdGetPriority();
97 97
 		chThdSetPriority(HIGHPRIO);
98 98
 	#endif
99 99
 	i2cAcquireBus(&I2CD1);
@@ -107,8 +107,8 @@ static GFXINLINE void release_bus(GDisplay *g) {
107 107
 	i2cReleaseBus(&I2CD1);
108 108
 }
109 109
 
110
-static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
111
-	uint8_t command[2];
110
+static GFXINLINE void write_cmd(GDisplay *g, gU8 cmd) {
111
+	gU8 command[2];
112 112
 	(void) g;
113 113
 
114 114
 	command[0] = 0x00;		// Co = 0, D/C = 0
@@ -119,7 +119,7 @@ static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
119 119
 	i2cStop(&I2CD1);
120 120
 }
121 121
 
122
-static GFXINLINE void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
122
+static GFXINLINE void write_data(GDisplay *g, gU8* data, gU16 length) {
123 123
 	(void) g;
124 124
 
125 125
 	i2cStart(&I2CD1, &i2cconfig);

+ 4 - 4
boards/addons/gdisp/board_SSD1963_fsmc.h

@@ -32,8 +32,8 @@ static const LCD_Parameters	DisplayTimings[] = {
32 32
 //	set g->board to that structure.
33 33
 
34 34
 /* Using FSMC A16 as RS */
35
-#define GDISP_REG              (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
36
-#define GDISP_RAM              (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
35
+#define GDISP_REG              (*((volatile gU16 *) 0x60000000)) /* RS = 0 */
36
+#define GDISP_RAM              (*((volatile gU16 *) 0x60020000)) /* RS = 1 */
37 37
 
38 38
 static GFXINLINE void init_board(GDisplay *g) {
39 39
 
@@ -94,12 +94,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
94 94
 	(void) g;
95 95
 }
96 96
 
97
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
97
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
98 98
 	(void) g;
99 99
 	GDISP_REG = index;
100 100
 }
101 101
 
102
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
102
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
103 103
 	(void) g;
104 104
 	GDISP_RAM = data;
105 105
 }

+ 2 - 2
boards/addons/gdisp/board_SSD1963_gpio.h

@@ -87,14 +87,14 @@ static GFXINLINE void release_bus(GDisplay *g) {
87 87
 	Clr_CS;
88 88
 }
89 89
 
90
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
90
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
91 91
 	(void) g;
92 92
 	Set_RS; Clr_RD; Set_WR;
93 93
 	palWritePort(GDISP_DATA_PORT, index);
94 94
 	Clr_WR;
95 95
 }
96 96
 
97
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
97
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
98 98
 	(void) g;
99 99
 	Clr_RS; Clr_RD; Set_WR;
100 100
 	palWritePort(GDISP_DATA_PORT, data);

+ 3 - 3
boards/addons/gdisp/board_UC8173_nordic_nrf52_sdk11.h

@@ -94,7 +94,7 @@ static GFXINLINE void release_bus(GDisplay* g)
94 94
 	nrf_gpio_pin_set(PIN_CS);
95 95
 }
96 96
 
97
-static GFXINLINE void write_cmd(GDisplay* g, uint8_t cmd)
97
+static GFXINLINE void write_cmd(GDisplay* g, gU8 cmd)
98 98
 {
99 99
 	(void)g;
100 100
 
@@ -102,7 +102,7 @@ static GFXINLINE void write_cmd(GDisplay* g, uint8_t cmd)
102 102
 	nrf_drv_spi_transfer(&spi, &cmd, 1, 0, 0);
103 103
 }
104 104
 
105
-static GFXINLINE void write_data(GDisplay* g, uint8_t data)
105
+static GFXINLINE void write_data(GDisplay* g, gU8 data)
106 106
 {
107 107
 	(void)g;
108 108
 	
@@ -110,7 +110,7 @@ static GFXINLINE void write_data(GDisplay* g, uint8_t data)
110 110
 	nrf_drv_spi_transfer(&spi, &data, 1, 0, 0);
111 111
 }
112 112
 
113
-static GFXINLINE void write_data_burst(GDisplay* g, uint8_t* data, uint8_t length)
113
+static GFXINLINE void write_data_burst(GDisplay* g, gU8* data, gU8 length)
114 114
 {
115 115
 	(void)g;
116 116
 	

+ 4 - 4
boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_olimex_stm32_e407.h

@@ -66,14 +66,14 @@ static GFXINLINE void release_bus(GMouse* m) {
66 66
     //TOUCHSCREEN_SPI_EPILOGUE();
67 67
 }
68 68
 
69
-static GFXINLINE uint16_t read_value(GMouse* m, uint16_t port) {
70
-    static uint8_t txbuf[3] = {0};
71
-    static uint8_t rxbuf[3] = {0};
69
+static GFXINLINE gU16 read_value(GMouse* m, gU16 port) {
70
+    static gU8 txbuf[3] = {0};
71
+    static gU8 rxbuf[3] = {0};
72 72
 	(void)		m;
73 73
 
74 74
     txbuf[0] = port;
75 75
     spiExchange(&SPID2, 3, txbuf, rxbuf);
76
-    return ((uint16_t)rxbuf[1] << 5) | (rxbuf[2] >> 3);
76
+    return ((gU16)rxbuf[1] << 5) | (rxbuf[2] >> 3);
77 77
 }
78 78
 
79 79
 #endif /* _GINPUT_LLD_MOUSE_BOARD_H */

+ 4 - 4
boards/addons/ginput/touch/ADS7843/ginput_lld_mouse_board_st_stm32f4_discovery.h

@@ -80,15 +80,15 @@ static GFXINLINE void release_bus(GMouse* m) {
80 80
 	spiReleaseBus(&SPID2);
81 81
 }
82 82
 
83
-static GFXINLINE uint16_t read_value(GMouse* m, uint16_t port) {
84
-	static uint8_t txbuf[3] = {0};
85
-	static uint8_t rxbuf[3] = {0};
83
+static GFXINLINE gU16 read_value(GMouse* m, gU16 port) {
84
+	static gU8 txbuf[3] = {0};
85
+	static gU8 rxbuf[3] = {0};
86 86
 	(void)		m;
87 87
 
88 88
 	txbuf[0] = port;
89 89
 	spiExchange(&SPID2, 3, txbuf, rxbuf);
90 90
 
91
-	return ((uint16_t)rxbuf[1] << 5) | (rxbuf[2] >> 3);
91
+	return ((gU16)rxbuf[1] << 5) | (rxbuf[2] >> 3);
92 92
 }
93 93
 
94 94
 #endif /* _GINPUT_LLD_MOUSE_BOARD_H */

+ 4 - 4
boards/addons/ginput/touch/ADS7843/stm32f4cube_hal.h

@@ -123,11 +123,11 @@ static GFXINLINE void release_bus(GMouse* m)
123 123
   HAL_GPIO_WritePin(GPIOA, GPIO_PIN_4, GPIO_PIN_SET);
124 124
 }
125 125
 
126
-static GFXINLINE uint16_t read_value(GMouse* m, uint16_t reg)
126
+static GFXINLINE gU16 read_value(GMouse* m, gU16 reg)
127 127
 {
128
-  uint8_t txbuf[3] = {0, 0, 0};
129
-  uint8_t rxbuf[3] = {0, 0, 0};
130
-  uint16_t ret;
128
+  gU8 txbuf[3] = {0, 0, 0};
129
+  gU8 rxbuf[3] = {0, 0, 0};
130
+  gU16 ret;
131 131
 
132 132
   (void)m;
133 133
 

+ 2 - 2
boards/base/Altera-MAX10-Neek/board_alteraframereader.h

@@ -10,13 +10,13 @@
10 10
 #define FRAMEREADER_BASE        ALT_VIP_VFR_0_BASE
11 11
 
12 12
 #if GDISP_NEED_CONTROL
13
-	static void board_backlight(GDisplay* g, uint8_t percent)
13
+	static void board_backlight(GDisplay* g, gU8 percent)
14 14
 	{
15 15
 		(void) g;
16 16
 		(void) percent;
17 17
 	}
18 18
 
19
-	static void board_contrast(GDisplay* g, uint8_t percent)
19
+	static void board_contrast(GDisplay* g, gU8 percent)
20 20
 	{
21 21
 		(void) g;
22 22
 		(void) percent;

+ 7 - 7
boards/base/Altera-MAX10-Neek/gmouse_lld_FT5316_board.h

@@ -76,29 +76,29 @@ static gBool init_board(GMouse* m, unsigned instance)
76 76
 	return gTrue;
77 77
 }
78 78
 
79
-static void write_reg(GMouse* m, uint8_t reg, uint8_t val)
79
+static void write_reg(GMouse* m, gU8 reg, gU8 val)
80 80
 {
81 81
 	(void)m;
82 82
 
83 83
 	device_write(FT5316_I2C_SLAVE_ADDRESS, reg, val);
84 84
 }
85 85
 
86
-static uint8_t read_byte(GMouse* m, uint8_t reg)
86
+static gU8 read_byte(GMouse* m, gU8 reg)
87 87
 {
88 88
 	(void)m;
89
-	uint8_t ret = 0;
89
+	gU8 ret = 0;
90 90
 
91
-	ret = (uint8_t)device_read(FT5316_I2C_SLAVE_ADDRESS, reg);
91
+	ret = (gU8)device_read(FT5316_I2C_SLAVE_ADDRESS, reg);
92 92
 
93 93
 	return ret;
94 94
 }
95 95
 
96
-static uint16_t read_word(GMouse* m, uint8_t reg)
96
+static gU16 read_word(GMouse* m, gU8 reg)
97 97
 {
98 98
 	(void)m;
99
-	uint16_t ret = 0;
99
+	gU16 ret = 0;
100 100
 
101
-	ret = (uint16_t)device_read(FT5316_I2C_SLAVE_ADDRESS, reg);
101
+	ret = (gU16)device_read(FT5316_I2C_SLAVE_ADDRESS, reg);
102 102
 
103 103
 	return ret;
104 104
 }

+ 4 - 4
boards/base/ArduinoTinyScreen/gfx/board_SSD1331.cpp

@@ -26,9 +26,9 @@
26 26
 // Wire address of the SX1505 chip
27 27
 #define GPIO_ADDR			0x20
28 28
 
29
-static void writeGPIO(uint8_t regAddr, uint8_t regData)
29
+static void writeGPIO(gU8 regAddr, gU8 regData)
30 30
 {
31
-  uint8_t oldTWBR=TWBR;
31
+  gU8 oldTWBR=TWBR;
32 32
   TWBR=0;
33 33
   Wire.beginTransmission(GPIO_ADDR + LCD_BOARD_ID);
34 34
   Wire.write(regAddr); 
@@ -69,7 +69,7 @@ void SSD1331_releasebus(void) {
69 69
 	isDataMode = isCmdMode = false;
70 70
 }
71 71
 
72
-void SSD1331_write_cmd(uint8_t cmd) {
72
+void SSD1331_write_cmd(gU8 cmd) {
73 73
 	if (!isCmdMode) {
74 74
 		writeGPIO(GPIO_RegData,GPIO_CMD_START);
75 75
 		isDataMode = false;
@@ -78,7 +78,7 @@ void SSD1331_write_cmd(uint8_t cmd) {
78 78
 	SPI.transfer(cmd);
79 79
 }
80 80
 
81
-void SSD1331_write_data(uint8_t data) {
81
+void SSD1331_write_data(gU8 data) {
82 82
 	if (!isDataMode) {
83 83
 		writeGPIO(GPIO_RegData,GPIO_DATA_START);
84 84
 		isDataMode = true;

+ 2 - 2
boards/base/ArduinoTinyScreen/gfx/board_SSD1331.h

@@ -25,8 +25,8 @@ void SSD1331_init_board(void);
25 25
 void SSD1331_setpin_reset(int state);
26 26
 void SSD1331_aquirebus(void);
27 27
 void SSD1331_releasebus(void);
28
-void SSD1331_write_cmd(uint8_t cmd);
29
-void SSD1331_write_data(uint8_t data);
28
+void SSD1331_write_cmd(gU8 cmd);
29
+void SSD1331_write_data(gU8 data);
30 30
 
31 31
 #ifdef __cplusplus
32 32
 }

+ 6 - 6
boards/base/Embest-STM32-DMSTF4BB/board_SSD2119.h

@@ -12,8 +12,8 @@
12 12
 //	set g->board to that structure.
13 13
 
14 14
 /* Using FSMC A19 (PE3) as DC */
15
-#define GDISP_REG (*((volatile uint16_t *) 0x60000000)) /* DC = 0 */
16
-#define GDISP_RAM (*((volatile uint16_t *) 0x60100000)) /* DC = 1 */
15
+#define GDISP_REG (*((volatile gU16 *) 0x60000000)) /* DC = 0 */
16
+#define GDISP_RAM (*((volatile gU16 *) 0x60100000)) /* DC = 1 */
17 17
 #define GDISP_DMA_STREAM STM32_DMA2_STREAM6
18 18
 
19 19
 #define SET_RST palSetPad(GPIOD, 3);
@@ -108,7 +108,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
108 108
 	}
109 109
 }
110 110
 
111
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
111
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
112 112
 	(void) g;
113 113
 	pwmEnableChannel(&PWMD4, 1, percent);
114 114
 }
@@ -121,12 +121,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
121 121
 	(void) g;
122 122
 }
123 123
 
124
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
124
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
125 125
 	(void) g;
126 126
 	GDISP_REG = index;
127 127
 }
128 128
 
129
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
129
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
130 130
 	(void) g;
131 131
 	GDISP_RAM = data;
132 132
 }
@@ -139,7 +139,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
139 139
 	(void) g;
140 140
 }
141 141
 
142
-static GFXINLINE uint16_t read_data(GDisplay *g) {
142
+static GFXINLINE gU16 read_data(GDisplay *g) {
143 143
 	(void) g;
144 144
 	return GDISP_RAM;
145 145
 }

+ 7 - 7
boards/base/Embest-STM32-DMSTF4BB/gmouse_lld_STMPE811_board.h

@@ -77,8 +77,8 @@ static GFXINLINE void release_bus(GMouse* m) {
77 77
 
78 78
 }
79 79
 
80
-static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
81
-	uint8_t		txbuf[2];
80
+static void write_reg(GMouse* m, gU8 reg, gU8 val) {
81
+	gU8		txbuf[2];
82 82
 	(void)		m;
83 83
 
84 84
 	txbuf[0] = reg;
@@ -89,8 +89,8 @@ static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
89 89
 	i2cReleaseBus(&I2CD1);
90 90
 }
91 91
 
92
-static uint8_t read_byte(GMouse* m, uint8_t reg) {
93
-	uint8_t		rxbuf[1];
92
+static gU8 read_byte(GMouse* m, gU8 reg) {
93
+	gU8		rxbuf[1];
94 94
 	(void)		m;
95 95
 
96 96
 	rxbuf[0] = 0;
@@ -102,8 +102,8 @@ static uint8_t read_byte(GMouse* m, uint8_t reg) {
102 102
 	return rxbuf[0];
103 103
 }
104 104
 
105
-static uint16_t read_word(GMouse* m, uint8_t reg) {
106
-	uint8_t		rxbuf[2];
105
+static gU16 read_word(GMouse* m, gU8 reg) {
106
+	gU8		rxbuf[2];
107 107
 	(void)		m;
108 108
 
109 109
 	rxbuf[0] = 0;
@@ -113,7 +113,7 @@ static uint16_t read_word(GMouse* m, uint8_t reg) {
113 113
 	i2cMasterTransmitTimeout(&I2CD1, STMPE811_ADDR, &reg, 1, rxbuf, 2, MS2ST(STMPE811_TIMEOUT));
114 114
 	i2cReleaseBus(&I2CD1);
115 115
 
116
-	return (((uint16_t)rxbuf[0]) << 8) | rxbuf[1];
116
+	return (((gU16)rxbuf[0]) << 8) | rxbuf[1];
117 117
 }
118 118
 
119 119
 #endif /* _GINPUT_LLD_MOUSE_BOARD_H */

+ 4 - 4
boards/base/FireBull-STM32F103-FB/board_SSD1289.h

@@ -56,7 +56,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state)
56 56
 	/* Nothing to do here - reset pin tied to Vcc */
57 57
 }
58 58
 
59
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent)
59
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent)
60 60
 {
61 61
 	(void) g;
62 62
 	(void) percent;
@@ -74,7 +74,7 @@ static GFXINLINE void release_bus(GDisplay *g)
74 74
 	(void) g;
75 75
 }
76 76
 
77
-static GFXINLINE void write_index(GDisplay *g, uint16_t index)
77
+static GFXINLINE void write_index(GDisplay *g, gU16 index)
78 78
 {
79 79
 	(void) g;
80 80
 
@@ -85,7 +85,7 @@ static GFXINLINE void write_index(GDisplay *g, uint16_t index)
85 85
 	SET_RS;
86 86
 }
87 87
 
88
-static GFXINLINE void write_data(GDisplay *g, uint16_t data)
88
+static GFXINLINE void write_data(GDisplay *g, gU16 data)
89 89
 {
90 90
 	(void) g;
91 91
 
@@ -112,7 +112,7 @@ static GFXINLINE void setwritemode(GDisplay *g)
112 112
 	palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
113 113
 }
114 114
 
115
-static GFXINLINE uint16_t read_data(GDisplay *g) {
115
+static GFXINLINE gU16 read_data(GDisplay *g) {
116 116
 	(void) g;
117 117
 
118 118
 	return palReadPort(GPIOE);

+ 4 - 4
boards/base/FireBull-STM32F103-FB/gmouse_lld_ADS7843_board.h

@@ -66,11 +66,11 @@ static GFXINLINE void release_bus(GMouse* m)
66 66
 	spiReleaseBus(&SPID1);
67 67
 }
68 68
 
69
-static GFXINLINE uint16_t read_value(GMouse* m, uint16_t port)
69
+static GFXINLINE gU16 read_value(GMouse* m, gU16 port)
70 70
 {
71
-    static uint8_t txbuf[3] = {0};
72
-    static uint8_t rxbuf[3] = {0};
73
-    uint16_t ret;
71
+    static gU8 txbuf[3] = {0};
72
+    static gU8 rxbuf[3] = {0};
73
+    gU16 ret;
74 74
 	(void)	m;
75 75
 
76 76
     txbuf[0] = port;

+ 6 - 6
boards/base/HY-MiniSTM32V/board_SSD1289.h

@@ -40,8 +40,8 @@ static const PWMConfig pwmcfg =
40 40
 /*
41 41
  * LCD_RS is on A16 (PD11)
42 42
  */
43
-#define GDISP_REG   (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
44
-#define GDISP_RAM   (*((volatile uint16_t *) 0x60020000)) /* RS = 1 */
43
+#define GDISP_REG   (*((volatile gU16 *) 0x60000000)) /* RS = 0 */
44
+#define GDISP_RAM   (*((volatile gU16 *) 0x60020000)) /* RS = 1 */
45 45
 /*
46 46
  * STM32_DMA1_STREAM7
47 47
  * NOTE: conflicts w/ USART2_TX, TIM2_CH2, TIM2_CH4, TIM4_UP, I2C1_RX in case
@@ -131,7 +131,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
131 131
   else {}
132 132
 }
133 133
 
134
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
134
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
135 135
   (void) g;
136 136
   if (percent > 100) { percent = 100; }
137 137
   pwmEnableChannel(&PWMD3, 1, percent);
@@ -145,12 +145,12 @@ static GFXINLINE void release_bus(GDisplay *g) {
145 145
   (void) g;
146 146
 }
147 147
 
148
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
148
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
149 149
   (void) g;
150 150
   GDISP_REG = index;
151 151
 }
152 152
 
153
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
153
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
154 154
   (void) g;
155 155
   GDISP_RAM = data;
156 156
 }
@@ -163,7 +163,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
163 163
   (void) g;
164 164
 }
165 165
 
166
-static GFXINLINE uint16_t read_data(GDisplay *g) {
166
+static GFXINLINE gU16 read_data(GDisplay *g) {
167 167
   (void) g;
168 168
   return GDISP_RAM;
169 169
 }

+ 4 - 4
boards/base/HY-MiniSTM32V/gmouse_lld_ADS7843_board.h

@@ -83,11 +83,11 @@ static GFXINLINE void release_bus(GMouse* m) {
83 83
   spiReleaseBus(&SPID1);
84 84
 }
85 85
 
86
-static GFXINLINE uint16_t read_value(GMouse* m, uint16_t port) {
86
+static GFXINLINE gU16 read_value(GMouse* m, gU16 port) {
87 87
   (void)m;
88
-  static uint8_t txbuf[3] = {0};
89
-  static uint8_t rxbuf[3] = {0};
90
-  uint16_t ret;
88
+  static gU8 txbuf[3] = {0};
89
+  static gU8 rxbuf[3] = {0};
90
+  gU16 ret;
91 91
 
92 92
   txbuf[0] = port;
93 93
   spiExchange(&SPID1, 3, txbuf, rxbuf);

+ 2 - 2
boards/base/Linux-Framebuffer/board_framebuffer.h

@@ -203,12 +203,12 @@
203 203
 	#endif
204 204
 
205 205
 	#if GDISP_NEED_CONTROL
206
-		static void board_backlight(GDisplay *g, uint8_t percent) {
206
+		static void board_backlight(GDisplay *g, gU8 percent) {
207 207
 			(void) g;
208 208
 			(void) percent;
209 209
 		}
210 210
 
211
-		static void board_contrast(GDisplay *g, uint8_t percent) {
211
+		static void board_contrast(GDisplay *g, gU8 percent) {
212 212
 			(void) g;
213 213
 			(void) percent;
214 214
 		}

+ 5 - 5
boards/base/Marlin/board_RA8875.h

@@ -15,8 +15,8 @@
15 15
 
16 16
 // For a multiple display configuration we would put all this in a structure and then
17 17
 // set g->board to that structure.
18
-#define GDISP_RAM              (*((volatile uint16_t *) 0x68000000)) /* RS = 0 */
19
-#define GDISP_REG              (*((volatile uint16_t *) 0x68020000)) /* RS = 1 */
18
+#define GDISP_RAM              (*((volatile gU16 *) 0x68000000)) /* RS = 0 */
19
+#define GDISP_REG              (*((volatile gU16 *) 0x68020000)) /* RS = 1 */
20 20
 #define FSMC_BANK				4
21 21
 
22 22
 
@@ -83,13 +83,13 @@ static GFXINLINE void release_bus(GDisplay *g) {
83 83
 	(void) g;
84 84
 }
85 85
 
86
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
86
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
87 87
 	(void) g;
88 88
 
89 89
 	GDISP_REG = index;
90 90
 }
91 91
 
92
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
92
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
93 93
 	(void) g;
94 94
 
95 95
 	GDISP_RAM = data;
@@ -103,7 +103,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
103 103
 	(void) g;
104 104
 }
105 105
 
106
-static GFXINLINE uint16_t read_data(GDisplay *g) {
106
+static GFXINLINE gU16 read_data(GDisplay *g) {
107 107
 	(void) g;
108 108
 
109 109
 	return GDISP_RAM;

+ 7 - 7
boards/base/Marlin/gmouse_lld_FT5x06_board.h

@@ -51,8 +51,8 @@ static GFXINLINE void release_bus(GMouse* m) {
51 51
 
52 52
 }
53 53
 
54
-static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
55
-	uint8_t txbuf[2];
54
+static void write_reg(GMouse* m, gU8 reg, gU8 val) {
55
+	gU8 txbuf[2];
56 56
 	(void)		m;
57 57
 
58 58
 	txbuf[0] = reg;
@@ -63,8 +63,8 @@ static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
63 63
 	i2cReleaseBus(&I2CD2);
64 64
 }
65 65
 
66
-static uint8_t read_byte(GMouse* m, uint8_t reg) {
67
-	uint8_t		rxbuf[1];
66
+static gU8 read_byte(GMouse* m, gU8 reg) {
67
+	gU8		rxbuf[1];
68 68
 	(void)		m;
69 69
 
70 70
 	rxbuf[0] = 0;
@@ -76,8 +76,8 @@ static uint8_t read_byte(GMouse* m, uint8_t reg) {
76 76
 	return rxbuf[0];
77 77
 }
78 78
 
79
-static uint16_t read_word(GMouse* m, uint8_t reg) {
80
-	uint8_t		rxbuf[2];
79
+static gU16 read_word(GMouse* m, gU8 reg) {
80
+	gU8		rxbuf[2];
81 81
 	(void)		m;
82 82
 
83 83
 	rxbuf[0] = 0;
@@ -87,7 +87,7 @@ static uint16_t read_word(GMouse* m, uint8_t reg) {
87 87
 	i2cMasterTransmitTimeout(&I2CD2, FT5x06_ADDR, &reg, 1, rxbuf, 2, MS2ST(FT5x06_TIMEOUT));
88 88
 	i2cReleaseBus(&I2CD2);
89 89
 
90
-	return (((uint16_t)rxbuf[0]) << 8) | rxbuf[1];
90
+	return (((gU16)rxbuf[0]) << 8) | rxbuf[1];
91 91
 }
92 92
 
93 93
 #endif /* _GINPUT_LLD_MOUSE_BOARD_H */

+ 13 - 13
boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/flash_memory.c

@@ -19,10 +19,10 @@ static const SPIConfig flash_spicfg = {
19 19
 };
20 20
 
21 21
 bool flash_is_write_busy(void) {
22
-  static uint8_t is_write_busy_cmd[1];
22
+  static gU8 is_write_busy_cmd[1];
23 23
   is_write_busy_cmd[0] = _SERIAL_FLASH_CMD_RDSR;
24 24
   
25
-  uint8_t result[1];
25
+  gU8 result[1];
26 26
 
27 27
   spiAcquireBus(&SPID3);
28 28
   spiStart(&SPID3, &flash_spicfg);
@@ -44,9 +44,9 @@ void flash_write_enable(void) {
44 44
   spiReleaseBus(&SPID3);
45 45
 }
46 46
 
47
-void flash_sector_erase(uint32_t sector) {
47
+void flash_sector_erase(gU32 sector) {
48 48
   flash_write_enable();
49
-  static uint8_t sector_erase_cmd[4];
49
+  static gU8 sector_erase_cmd[4];
50 50
   sector_erase_cmd[0] = _SERIAL_FLASH_CMD_SER;
51 51
   sector_erase_cmd[1] = (sector >> 16) & 0xFF;
52 52
   sector_erase_cmd[2] = (sector >> 8) & 0xFF;
@@ -64,8 +64,8 @@ void flash_sector_erase(uint32_t sector) {
64 64
   while(flash_is_write_busy());
65 65
 }
66 66
 
67
-void flash_read(uint32_t address, size_t bytes, uint8_t *out) {
68
-  static uint8_t sector_read_cmd[4];
67
+void flash_read(gU32 address, gMemSize bytes, gU8 *out) {
68
+  static gU8 sector_read_cmd[4];
69 69
   sector_read_cmd[0] = _SERIAL_FLASH_CMD_READ;
70 70
   sector_read_cmd[1] = (address >> 16) & 0xFF;
71 71
   sector_read_cmd[2] = (address >> 8) & 0xFF;
@@ -80,8 +80,8 @@ void flash_read(uint32_t address, size_t bytes, uint8_t *out) {
80 80
   spiReleaseBus(&SPID3);
81 81
 }
82 82
 
83
-void flash_write(uint32_t address, size_t bytes, const uint8_t *data) {
84
-  static uint8_t flash_write_cmd[4];
83
+void flash_write(gU32 address, gMemSize bytes, const gU8 *data) {
84
+  static gU8 flash_write_cmd[4];
85 85
 
86 86
   flash_write_enable();
87 87
 
@@ -103,21 +103,21 @@ void flash_write(uint32_t address, size_t bytes, const uint8_t *data) {
103 103
 }
104 104
 
105 105
 bool flash_tp_calibrated(void) {
106
-  uint8_t out[1];
106
+  gU8 out[1];
107 107
   flash_read(0x0F0000, 1, out);
108 108
 
109 109
   return (out[0] == 0x01);
110 110
 }
111 111
 
112
-void flash_tp_calibration_save(uint16_t instance, const uint8_t *calbuf, size_t sz) {
112
+void flash_tp_calibration_save(gU16 instance, const gU8 *calbuf, gMemSize sz) {
113 113
   if (instance) return;
114 114
   flash_sector_erase(0x0F0000);
115
-  uint8_t calibrated = 0x01;
115
+  gU8 calibrated = 0x01;
116 116
   flash_write(0x0F0000, 1, &calibrated);
117 117
   flash_write(0x0F0001, sz, calbuf);
118 118
 }
119
-const char *flash_tp_calibration_load(uint16_t instance) {
120
-  static uint8_t foo[24];
119
+const char *flash_tp_calibration_load(gU16 instance) {
120
+  static gU8 foo[24];
121 121
 
122 122
   if (instance) return 0;
123 123
   if (!flash_tp_calibrated()) return 0;

+ 5 - 5
boards/base/Mikromedia-Plus-STM32-M4/ChibiOS_Board/flash_memory.h

@@ -1,6 +1,6 @@
1
-void flash_sector_erase(uint32_t sector);
2
-void flash_read(uint32_t address, size_t bytes, uint8_t *out);
3
-void flash_write(uint32_t address, size_t bytes, const uint8_t *data);
1
+void flash_sector_erase(gU32 sector);
2
+void flash_read(gU32 address, gMemSize bytes, gU8 *out);
3
+void flash_write(gU32 address, gMemSize bytes, const gU8 *data);
4 4
 bool flash_tp_calibrated(void);
5
-void flash_tp_calibration_save(uint16_t instance, const uint8_t *calbuf, size_t sz);
6
-const char *flash_tp_calibration_load(uint16_t instance);
5
+void flash_tp_calibration_save(gU16 instance, const gU8 *calbuf, gMemSize sz);
6
+const char *flash_tp_calibration_load(gU16 instance);

+ 4 - 4
boards/base/Mikromedia-Plus-STM32-M4/board_SSD1963.h

@@ -87,7 +87,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
87 87
 	SET_CS;
88 88
 }
89 89
 
90
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
90
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
91 91
 	(void) g;
92 92
 
93 93
 	CLR_DC;
@@ -97,7 +97,7 @@ static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
97 97
 	SET_DC;
98 98
 }
99 99
 
100
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
100
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
101 101
 	(void) g;
102 102
 
103 103
 	palWriteBus(&busDataLo, (data & 0xFF));
@@ -117,8 +117,8 @@ static GFXINLINE void setwritemode(GDisplay *g) {
117 117
 	palSetBusMode(&busDataHi, PAL_MODE_OUTPUT_PUSHPULL);
118 118
 }
119 119
 
120
-static GFXINLINE uint16_t read_data(GDisplay *g) {
121
-	uint16_t data;
120
+static GFXINLINE gU16 read_data(GDisplay *g) {
121
+	gU16 data;
122 122
 	(void) g;
123 123
 
124 124
 	CLR_RD;

+ 7 - 7
boards/base/Mikromedia-Plus-STM32-M4/gmouse_lld_STMPE610_board.h

@@ -77,8 +77,8 @@ static GFXINLINE void release_bus(GMouse* m) {
77 77
 
78 78
 }
79 79
 
80
-static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
81
-	uint8_t		txbuf[2];
80
+static void write_reg(GMouse* m, gU8 reg, gU8 val) {
81
+	gU8		txbuf[2];
82 82
 	(void)		m;
83 83
 
84 84
 	txbuf[0] = reg;
@@ -89,8 +89,8 @@ static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
89 89
 	i2cReleaseBus(&I2CD1);
90 90
 }
91 91
 
92
-static uint8_t read_byte(GMouse* m, uint8_t reg) {
93
-	uint8_t		rxbuf[1];
92
+static gU8 read_byte(GMouse* m, gU8 reg) {
93
+	gU8		rxbuf[1];
94 94
 	(void)		m;
95 95
 
96 96
 	rxbuf[0] = 0;
@@ -102,8 +102,8 @@ static uint8_t read_byte(GMouse* m, uint8_t reg) {
102 102
 	return rxbuf[0];
103 103
 }
104 104
 
105
-static uint16_t read_word(GMouse* m, uint8_t reg) {
106
-	uint8_t		rxbuf[2];
105
+static gU16 read_word(GMouse* m, gU8 reg) {
106
+	gU8		rxbuf[2];
107 107
 	(void)		m;
108 108
 
109 109
 	rxbuf[0] = 0;
@@ -113,7 +113,7 @@ static uint16_t read_word(GMouse* m, uint8_t reg) {
113 113
 	i2cMasterTransmitTimeout(&I2CD1, STMPE610_ADDR, &reg, 1, rxbuf, 2, MS2ST(STMPE610_TIMEOUT));
114 114
 	i2cReleaseBus(&I2CD1);
115 115
 
116
-	return (((uint16_t)rxbuf[0]) << 8) | rxbuf[1];
116
+	return (((gU16)rxbuf[0]) << 8) | rxbuf[1];
117 117
 }
118 118
 
119 119
 #endif /* _GINPUT_LLD_MOUSE_BOARD_H */

+ 13 - 13
boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/flash_memory.c

@@ -19,10 +19,10 @@ static const SPIConfig flash_spicfg = {
19 19
 };
20 20
 
21 21
 bool flash_is_write_busy(void) {
22
-  static uint8_t is_write_busy_cmd[1];
22
+  static gU8 is_write_busy_cmd[1];
23 23
   is_write_busy_cmd[0] = _SERIAL_FLASH_CMD_RDSR;
24 24
   
25
-  uint8_t result[1];
25
+  gU8 result[1];
26 26
 
27 27
   spiAcquireBus(&SPID3);
28 28
   spiStart(&SPID3, &flash_spicfg);
@@ -44,9 +44,9 @@ void flash_write_enable(void) {
44 44
   spiReleaseBus(&SPID3);
45 45
 }
46 46
 
47
-void flash_sector_erase(uint32_t sector) {
47
+void flash_sector_erase(gU32 sector) {
48 48
   flash_write_enable();
49
-  static uint8_t sector_erase_cmd[4];
49
+  static gU8 sector_erase_cmd[4];
50 50
   sector_erase_cmd[0] = _SERIAL_FLASH_CMD_SER;
51 51
   sector_erase_cmd[1] = (sector >> 16) & 0xFF;
52 52
   sector_erase_cmd[2] = (sector >> 8) & 0xFF;
@@ -64,8 +64,8 @@ void flash_sector_erase(uint32_t sector) {
64 64
   while(flash_is_write_busy());
65 65
 }
66 66
 
67
-void flash_read(uint32_t address, size_t bytes, uint8_t *out) {
68
-  static uint8_t sector_read_cmd[4];
67
+void flash_read(gU32 address, gMemSize bytes, gU8 *out) {
68
+  static gU8 sector_read_cmd[4];
69 69
   sector_read_cmd[0] = _SERIAL_FLASH_CMD_READ;
70 70
   sector_read_cmd[1] = (address >> 16) & 0xFF;
71 71
   sector_read_cmd[2] = (address >> 8) & 0xFF;
@@ -80,8 +80,8 @@ void flash_read(uint32_t address, size_t bytes, uint8_t *out) {
80 80
   spiReleaseBus(&SPID3);
81 81
 }
82 82
 
83
-void flash_write(uint32_t address, size_t bytes, const uint8_t *data) {
84
-  static uint8_t flash_write_cmd[4];
83
+void flash_write(gU32 address, gMemSize bytes, const gU8 *data) {
84
+  static gU8 flash_write_cmd[4];
85 85
 
86 86
   flash_write_enable();
87 87
 
@@ -103,21 +103,21 @@ void flash_write(uint32_t address, size_t bytes, const uint8_t *data) {
103 103
 }
104 104
 
105 105
 bool flash_tp_calibrated(void) {
106
-  uint8_t out[1];
106
+  gU8 out[1];
107 107
   flash_read(0x0F0000, 1, out);
108 108
 
109 109
   return (out[0] == 0x01);
110 110
 }
111 111
 
112
-void flash_tp_calibration_save(uint16_t instance, const uint8_t *calbuf, size_t sz) {
112
+void flash_tp_calibration_save(gU16 instance, const gU8 *calbuf, gMemSize sz) {
113 113
   if (instance) return;
114 114
   flash_sector_erase(0x0F0000);
115
-  uint8_t calibrated = 0x01;
115
+  gU8 calibrated = 0x01;
116 116
   flash_write(0x0F0000, 1, &calibrated);
117 117
   flash_write(0x0F0001, sz, calbuf);
118 118
 }
119
-const char *flash_tp_calibration_load(uint16_t instance) {
120
-  static uint8_t foo[24];
119
+const char *flash_tp_calibration_load(gU16 instance) {
120
+  static gU8 foo[24];
121 121
 
122 122
   if (instance) return 0;
123 123
   if (!flash_tp_calibrated()) return 0;

+ 5 - 5
boards/base/Mikromedia-STM32-M4-ILI9341/ChibiOS_Board/flash_memory.h

@@ -1,6 +1,6 @@
1
-void flash_sector_erase(uint32_t sector);
2
-void flash_read(uint32_t address, size_t bytes, uint8_t *out);
3
-void flash_write(uint32_t address, size_t bytes, const uint8_t *data);
1
+void flash_sector_erase(gU32 sector);
2
+void flash_read(gU32 address, gMemSize bytes, gU8 *out);
3
+void flash_write(gU32 address, gMemSize bytes, const gU8 *data);
4 4
 bool flash_tp_calibrated(void);
5
-void flash_tp_calibration_save(uint16_t instance, const uint8_t *calbuf, size_t sz);
6
-const char *flash_tp_calibration_load(uint16_t instance);
5
+void flash_tp_calibration_save(gU16 instance, const gU8 *calbuf, gMemSize sz);
6
+const char *flash_tp_calibration_load(gU16 instance);

+ 7 - 7
boards/base/Mikromedia-STM32-M4-ILI9341/board_ILI9341.h

@@ -49,7 +49,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
49 49
 	}
50 50
 }
51 51
 
52
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
52
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
53 53
 	(void) g;
54 54
 	// TODO: can probably pwm this
55 55
 	if(percent) {
@@ -76,19 +76,19 @@ static GFXINLINE void release_bus(GDisplay *g) {
76 76
  *
77 77
  * @notapi
78 78
  */
79
-static GFXINLINE void ili9341_delay(uint16_t dly) {
80
-  static uint16_t i;
79
+static GFXINLINE void ili9341_delay(gU16 dly) {
80
+  static gU16 i;
81 81
   for(i = 0; i < dly; i++)
82 82
     asm("nop");
83 83
 }
84 84
 
85
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
85
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
86 86
 	(void) g;
87 87
 	palWriteGroup(GPIOE, 0x00FF, 0, index);
88 88
 	CLR_RS; CLR_WR; ili9341_delay(1); SET_WR; ili9341_delay(1); SET_RS;
89 89
 }
90 90
 
91
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
91
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
92 92
 	(void) g;
93 93
 	palWriteGroup(GPIOE, 0x00FF, 0, data);
94 94
 	CLR_WR; ili9341_delay(1); SET_WR; ili9341_delay(1);
@@ -106,8 +106,8 @@ static GFXINLINE void setwritemode(GDisplay *g) {
106 106
 	palSetGroupMode(GPIOE, PAL_WHOLE_PORT, 0, PAL_MODE_OUTPUT_PUSHPULL);
107 107
 }
108 108
 
109
-static GFXINLINE uint16_t read_data(GDisplay *g) {
110
-	uint16_t	value;
109
+static GFXINLINE gU16 read_data(GDisplay *g) {
110
+	gU16	value;
111 111
 	(void) g;
112 112
 	CLR_RD;
113 113
 	value = palReadPort(GPIOE);

+ 3 - 3
boards/base/Olimex-SAM7EX256-GE12/board_Nokia6610GE12.h

@@ -141,7 +141,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
141 141
 		palSetPad(IOPORT1, PIOA_LCD_RESET);
142 142
 }
143 143
 
144
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
144
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
145 145
 	(void) g;
146 146
 	if (percent == 100) {
147 147
 		/* Turn the pin on - No PWM */
@@ -175,7 +175,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
175 175
 	(void) g;
176 176
 }
177 177
 
178
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
178
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
179 179
 	(void) g;
180 180
 	// wait for the previous transfer to complete
181 181
 	while(!(pSPI->SPI_SR & AT91C_SPI_TDRE));
@@ -183,7 +183,7 @@ static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
183 183
 	pSPI->SPI_TDR = index & 0xFF;
184 184
 }
185 185
 
186
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
186
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
187 187
 	(void) g;
188 188
 	// wait for the previous transfer to complete
189 189
 	while(!(pSPI->SPI_SR & AT91C_SPI_TDRE));

+ 3 - 3
boards/base/Olimex-SAM7EX256-GE8/board_Nokia6610GE8.h

@@ -139,7 +139,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
139 139
 		palSetPad(IOPORT1, PIOA_LCD_RESET);
140 140
 }
141 141
 
142
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
142
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
143 143
 	(void) g;
144 144
 	if (percent == 100) {
145 145
 		/* Turn the pin on - No PWM */
@@ -173,7 +173,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
173 173
 	(void) g;
174 174
 }
175 175
 
176
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
176
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
177 177
 	(void) g;
178 178
 	// wait for the previous transfer to start
179 179
 	while(!(pSPI->SPI_SR & AT91C_SPI_TDRE));
@@ -181,7 +181,7 @@ static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
181 181
 	pSPI->SPI_TDR = index & 0xFF;
182 182
 }
183 183
 
184
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
184
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
185 185
 	(void) g;
186 186
 	// wait for the previous transfer to start
187 187
 	while(!(pSPI->SPI_SR & AT91C_SPI_TDRE));

+ 4 - 4
boards/base/Olimex-SAM7EX256-GE8/board_SSD1306_i2c.h

@@ -81,7 +81,7 @@
81 81
 
82 82
 	#define I2C_WAITCOMPLETE()
83 83
 	#define I2C_WRITECMDBYTE(cmd)			{						\
84
-		uint8_t	data[2];											\
84
+		gU8	data[2];											\
85 85
 		data[0] = 0;												\
86 86
 		data[1] = cmd;												\
87 87
 		i2cMasterTransmitTimeout (UEXT_I2C, I2C_ADDRESS, data, 2, 0, 0, gDelayForever);	\
@@ -107,7 +107,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
107 107
 	(void) state;
108 108
 }
109 109
 
110
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
110
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
111 111
 	(void) g;
112 112
 	(void) percent;
113 113
 }
@@ -125,7 +125,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
125 125
 	I2C_RELEASEBUS();
126 126
 }
127 127
 
128
-static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
128
+static GFXINLINE void write_cmd(GDisplay *g, gU8 cmd) {
129 129
 	(void) g;
130 130
 
131 131
 	I2C_WAITCOMPLETE();
@@ -134,7 +134,7 @@ static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
134 134
 	I2C_WRITECMDBYTE(cmd);
135 135
 }
136 136
 
137
-static GFXINLINE void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
137
+static GFXINLINE void write_data(GDisplay *g, gU8* data, gU16 length) {
138 138
 	(void) g;
139 139
 
140 140
 	I2C_WAITCOMPLETE();

+ 5 - 5
boards/base/Olimex-SAM7EX256-GE8/board_SSD1306_spi.h

@@ -63,8 +63,8 @@
63 63
 
64 64
 	static void spi_delay(volatile unsigned long a) { while (a!=0) a--; }
65 65
 
66
-	static void spi_write(uint8_t data) {
67
-		uint8_t bit;
66
+	static void spi_write(gU8 data) {
67
+		gU8 bit;
68 68
 
69 69
 		for(bit = 0x80; bit; bit >>= 1) {
70 70
 			if(data & bit)
@@ -185,7 +185,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
185 185
 		PinSet(PORT_RESET, PIN_RESET);
186 186
 }
187 187
 
188
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
188
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
189 189
 	(void) g;
190 190
 	(void) percent;
191 191
 }
@@ -203,7 +203,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
203 203
 	SPI_RELEASEBUS();
204 204
 }
205 205
 
206
-static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
206
+static GFXINLINE void write_cmd(GDisplay *g, gU8 cmd) {
207 207
 	(void) g;
208 208
 
209 209
 	// Command mode please
@@ -213,7 +213,7 @@ static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
213 213
 	SPI_WRITEBYTE(cmd);
214 214
 }
215 215
 
216
-static GFXINLINE void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
216
+static GFXINLINE void write_data(GDisplay *g, gU8* data, gU16 length) {
217 217
 	(void) g;
218 218
 
219 219
 	// Data mode please

+ 5 - 5
boards/base/Olimex-SAM7EX256-GE8/board_SSD1331.h

@@ -63,8 +63,8 @@
63 63
 
64 64
 	static void spi_delay(volatile unsigned long a) { while (a!=0) a--; }
65 65
 
66
-	static void spi_write(uint8_t data) {
67
-		uint8_t bit;
66
+	static void spi_write(gU8 data) {
67
+		gU8 bit;
68 68
 
69 69
 		for(bit = 0x80; bit; bit >>= 1) {
70 70
 			if(data & bit)
@@ -182,7 +182,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
182 182
 		PinSet(PORT_RESET, PIN_RESET);
183 183
 }
184 184
 
185
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
185
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
186 186
 	(void) g;
187 187
 	(void) percent;
188 188
 }
@@ -200,7 +200,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
200 200
 	SPI_RELEASEBUS();
201 201
 }
202 202
 
203
-static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
203
+static GFXINLINE void write_cmd(GDisplay *g, gU8 cmd) {
204 204
 	(void) g;
205 205
 
206 206
 	// Command mode please
@@ -210,7 +210,7 @@ static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
210 210
 	SPI_WRITEBYTE(cmd);
211 211
 }
212 212
 
213
-static GFXINLINE void write_data(GDisplay *g, uint8_t data) {
213
+static GFXINLINE void write_data(GDisplay *g, gU8 data) {
214 214
 	(void) g;
215 215
 
216 216
 	// Data mode please

+ 5 - 5
boards/base/Olimex-SAM7EX256-GE8/board_TLS8204.h

@@ -49,8 +49,8 @@
49 49
 
50 50
 	static void spi_delay(volatile unsigned long a) { while (a!=0) a--; }
51 51
 
52
-	static void spi_write(uint8_t data) {
53
-		uint8_t bit;
52
+	static void spi_write(gU8 data) {
53
+		gU8 bit;
54 54
 
55 55
 		for(bit = 0x80; bit; bit >>= 1) {
56 56
 			if(data & bit)
@@ -171,7 +171,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
171 171
 		PinSet(PORT_RESET, PIN_RESET);
172 172
 }
173 173
 
174
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
174
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
175 175
 	(void) g;
176 176
 	(void) percent;
177 177
 }
@@ -189,7 +189,7 @@ static GFXINLINE void release_bus(GDisplay *g) {
189 189
 	SPI_RELEASEBUS();
190 190
 }
191 191
 
192
-static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
192
+static GFXINLINE void write_cmd(GDisplay *g, gU8 cmd) {
193 193
 	(void) g;
194 194
 
195 195
 	// Command mode please
@@ -199,7 +199,7 @@ static GFXINLINE void write_cmd(GDisplay *g, uint8_t cmd) {
199 199
 	SPI_WRITEBYTE(cmd);
200 200
 }
201 201
 
202
-static GFXINLINE void write_data(GDisplay *g, uint8_t* data, uint16_t length) {
202
+static GFXINLINE void write_data(GDisplay *g, gU8* data, gU16 length) {
203 203
 	(void) g;
204 204
 
205 205
 	// Data mode please

+ 3 - 3
boards/base/Olimex-SAM7EX256-GE8/gaudio_play_board.h

@@ -33,9 +33,9 @@ static GPTConfig gptcfg = {
33 33
   GPT_TRIGGER_NONE,				// trigger
34 34
 };
35 35
 
36
-static uint16_t		lastvalue;
36
+static gU16		lastvalue;
37 37
 
38
-static gBool gaudio_play_pwm_setup(uint32_t frequency, ArrayDataFormat format) {
38
+static gBool gaudio_play_pwm_setup(gU32 frequency, ArrayDataFormat format) {
39 39
 	if (format == ARRAY_DATA_10BITUNSIGNED)
40 40
 		pwmcfg.period = 1024;
41 41
 	else if (format == ARRAY_DATA_8BITUNSIGNED)
@@ -65,7 +65,7 @@ static void gaudio_play_pwm_stop(void) {
65 65
 	pwmStop(&PWMD1);
66 66
 }
67 67
 
68
-static void gaudio_play_pwm_setI(uint16_t value) {
68
+static void gaudio_play_pwm_setI(gU16 value) {
69 69
 	if (value != lastvalue) {
70 70
 		lastvalue = value;
71 71
 		pwmEnableChannelI(&PWMD1, 0, value);

+ 1 - 1
boards/base/Olimex-SAM7EX256-GE8/gaudio_record_board.h

@@ -30,7 +30,7 @@
30 30
 #define	GAUDIO_RECORD_MICROPHONE					0
31 31
 
32 32
 #ifdef GAUDIO_RECORD_IMPLEMENTATION
33
-	static uint32_t gaudio_gadc_physdevs[GAUDIO_RECORD_NUM_CHANNELS] = {
33
+	static gU32 gaudio_gadc_physdevs[GAUDIO_RECORD_NUM_CHANNELS] = {
34 34
 			GADC_PHYSDEV_MICROPHONE,
35 35
 			};
36 36
 #endif

+ 6 - 6
boards/base/Olimex-STM32-LCD/board_ILI9320.h

@@ -10,8 +10,8 @@
10 10
 
11 11
 // For a multiple display configuration we would put all this in a structure and then
12 12
 //	set g->board to that structure.
13
-#define GDISP_REG              (*((volatile uint16_t *) 0x60000000)) /* RS = 0 */
14
-#define GDISP_RAM              (*((volatile uint16_t *) 0x60100000)) /* RS = 1 */
13
+#define GDISP_REG              (*((volatile gU16 *) 0x60000000)) /* RS = 0 */
14
+#define GDISP_RAM              (*((volatile gU16 *) 0x60100000)) /* RS = 1 */
15 15
 
16 16
 static GFXINLINE void init_board(GDisplay *g) {
17 17
 
@@ -54,7 +54,7 @@ static GFXINLINE void setpin_reset(GDisplay *g, gBool state) {
54 54
 		palSetPad(GPIOE, GPIOE_TFT_RST);
55 55
 }
56 56
 
57
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
57
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
58 58
 	(void) g;
59 59
 
60 60
 	if(percent)
@@ -71,13 +71,13 @@ static GFXINLINE void release_bus(GDisplay *g) {
71 71
 	(void) g;
72 72
 }
73 73
 
74
-static GFXINLINE void write_index(GDisplay *g, uint16_t index) {
74
+static GFXINLINE void write_index(GDisplay *g, gU16 index) {
75 75
 	(void) g;
76 76
 
77 77
 	GDISP_REG = index;
78 78
 }
79 79
 
80
-static GFXINLINE void write_data(GDisplay *g, uint16_t data) {
80
+static GFXINLINE void write_data(GDisplay *g, gU16 data) {
81 81
 	(void) g;
82 82
 
83 83
 	GDISP_RAM = data;
@@ -91,7 +91,7 @@ static GFXINLINE void setwritemode(GDisplay *g) {
91 91
 	(void) g;
92 92
 }
93 93
 
94
-static GFXINLINE uint16_t read_data(GDisplay *g) {
94
+static GFXINLINE gU16 read_data(GDisplay *g) {
95 95
 	(void) g;
96 96
 
97 97
 	return GDISP_RAM;

+ 1 - 1
boards/base/Olimex-STM32-LCD/gmouse_lld_MCU_board.h

@@ -75,7 +75,7 @@ static gBool init_board(GMouse *m, unsigned driverinstance) {
75 75
 
76 76
 static gBool read_xyz(GMouse *m, GMouseReading *prd) {
77 77
 	adcsample_t samples[ADC_NUM_CHANNELS * ADC_BUF_DEPTH];
78
-	uint16_t val1, val2;
78
+	gU16 val1, val2;
79 79
 	(void)		m;
80 80
 
81 81
 	// No buttons and assume touch off

+ 5 - 5
boards/base/RaspberryPi/FreeRTOS/mmio.h

@@ -6,16 +6,16 @@
6 6
 #include <stdint.h>
7 7
  
8 8
 // write to MMIO register
9
-static GFXINLINE void mmio_write(uint32_t reg, uint32_t data) {
10
-    uint32_t *ptr = (uint32_t*)reg;
9
+static GFXINLINE void mmio_write(gU32 reg, gU32 data) {
10
+    gU32 *ptr = (gU32*)reg;
11 11
     asm volatile("str %[data], [%[reg]]"
12 12
 	     : : [reg]"r"(ptr), [data]"r"(data));
13 13
 }
14 14
  
15 15
 // read from MMIO register
16
-static GFXINLINE uint32_t mmio_read(uint32_t reg) {
17
-    uint32_t *ptr = (uint32_t*)reg;
18
-    uint32_t data;
16
+static GFXINLINE gU32 mmio_read(gU32 reg) {
17
+    gU32 *ptr = (gU32*)reg;
18
+    gU32 data;
19 19
     asm volatile("ldr %[data], [%[reg]]"
20 20
 		 : [data]"=r"(data) : [reg]"r"(ptr));
21 21
     return data;

+ 4 - 4
boards/base/RaspberryPi/FreeRTOS/uart.c

@@ -46,12 +46,12 @@ enum {
46 46
  
47 47
 /*
48 48
  * delay function
49
- * int32_t delay: number of cycles to delay
49
+ * gI32 delay: number of cycles to delay
50 50
  *
51 51
  * This just loops <delay> times in a way that the compiler
52 52
  * wont optimize away.
53 53
  */
54
-static void delay(int32_t count) {
54
+static void delay(gI32 count) {
55 55
     asm volatile("__delay_%=: subs %[count], %[count], #1; bne __delay_%=\n"
56 56
 	     : : [count]"r"(count) : "cc");
57 57
 }
@@ -102,9 +102,9 @@ void uart_init() {
102 102
  
103 103
 /*
104 104
  * Transmit a byte via UART0.
105
- * uint8_t Byte: byte to send.
105
+ * gU8 Byte: byte to send.
106 106
  */
107
-void uart_putc(uint8_t byte) {
107
+void uart_putc(gU8 byte) {
108 108
     // wait for UART to become ready to transmit
109 109
     while (1) {
110 110
         if (!(mmio_read(UART0_FR) & (1 << 5))) {

+ 2 - 2
boards/base/RaspberryPi/FreeRTOS/uart.h

@@ -12,9 +12,9 @@ void uart_init();
12 12
  
13 13
 /*
14 14
  * Transmit a byte via UART0.
15
- * uint8_t Byte: byte to send.
15
+ * gU8 Byte: byte to send.
16 16
  */
17
-void uart_putc(uint8_t byte);
17
+void uart_putc(gU8 byte);
18 18
  
19 19
 /*
20 20
  * print a string to the UART one character at a time

+ 12 - 12
boards/base/RaspberryPi/board_framebuffer.h

@@ -26,16 +26,16 @@
26 26
 	#include "rpi_mailbox.h"
27 27
 
28 28
 	typedef struct FrameBufferDescription {
29
-		uint32_t	width;
30
-		uint32_t	height;
31
-		uint32_t	vWidth;
32
-		uint32_t	vHeight;
33
-		uint32_t	pitch;
34
-		uint32_t	bitDepth;
35
-		uint32_t	x;
36
-		uint32_t	y;
29
+		gU32	width;
30
+		gU32	height;
31
+		gU32	vWidth;
32
+		gU32	vHeight;
33
+		gU32	pitch;
34
+		gU32	bitDepth;
35
+		gU32	x;
36
+		gU32	y;
37 37
 		void *		pointer;
38
-		uint32_t	size;
38
+		gU32	size;
39 39
 		} FrameBufferDescription;
40 40
 
41 41
 	static FrameBufferDescription FrameBufferInfo __attribute__((aligned (16))) = { 1024, 768, 1024, 768, 0, 24, 0, 0, 0, 0 };
@@ -49,7 +49,7 @@
49 49
 		FrameBufferInfo.vHeight = GDISP_SCREEN_HEIGHT;
50 50
 		FrameBufferInfo.bitDepth = LLDCOLOR_BITS;
51 51
 
52
-		rpi_writemailbox(1, 0x40000000 + (uint32_t) &FrameBufferInfo);
52
+		rpi_writemailbox(1, 0x40000000 + (gU32) &FrameBufferInfo);
53 53
 
54 54
 		if (rpi_readmailbox(1) != 0)
55 55
 			gfxHalt("Could not set display parameters")
@@ -70,12 +70,12 @@
70 70
 	#endif
71 71
 
72 72
 	#if GDISP_NEED_CONTROL
73
-		static void board_backlight(GDisplay *g, uint8_t percent) {
73
+		static void board_backlight(GDisplay *g, gU8 percent) {
74 74
 			(void) g;
75 75
 			(void) percent;
76 76
 		}
77 77
 
78
-		static void board_contrast(GDisplay *g, uint8_t percent) {
78
+		static void board_contrast(GDisplay *g, gU8 percent) {
79 79
 			(void) g;
80 80
 			(void) percent;
81 81
 		}

+ 7 - 7
boards/base/STM32F429i-Discovery/chibios/board_STM32LTDC.h

@@ -82,8 +82,8 @@ static void release_bus(GDisplay *g) {
82 82
 	spiUnselect(SPI_PORT);
83 83
 }
84 84
 
85
-static void write_index(GDisplay *g, uint8_t index) {
86
-	static uint8_t	sindex;
85
+static void write_index(GDisplay *g, gU8 index) {
86
+	static gU8	sindex;
87 87
 	(void) g;
88 88
 
89 89
 	palClearPad(DC_PORT, DC_PIN);
@@ -91,8 +91,8 @@ static void write_index(GDisplay *g, uint8_t index) {
91 91
 	spiSend(SPI_PORT, 1, &sindex);
92 92
 }
93 93
 
94
-static void write_data(GDisplay *g, uint8_t data) {
95
-	static uint8_t	sdata;
94
+static void write_data(GDisplay *g, gU8 data) {
95
+	static gU8	sdata;
96 96
 	(void) g;
97 97
 
98 98
 	palSetPad(DC_PORT, DC_PIN);
@@ -108,7 +108,7 @@ static void Init9341(GDisplay *g) {
108 108
 	#define REG_COMMAND		0x0100
109 109
 	#define REG_DELAY		0x0200
110 110
 
111
-	static const uint16_t initdata[] = {
111
+	static const gU16 initdata[] = {
112 112
 			REG_COMMAND | ILI9341_CMD_RESET,
113 113
 			REG_DELAY   | 5,
114 114
 			REG_COMMAND | ILI9341_CMD_DISPLAY_OFF,
@@ -152,7 +152,7 @@ static void Init9341(GDisplay *g) {
152 152
 			REG_COMMAND | ILI9341_SET_MEM
153 153
 	};
154 154
 
155
-	const uint16_t	*p;
155
+	const gU16	*p;
156 156
 
157 157
 	acquire_bus(g);
158 158
 	for(p = initdata; p < &initdata[sizeof(initdata)/sizeof(initdata[0])]; p++) {
@@ -206,7 +206,7 @@ static GFXINLINE void post_init_board(GDisplay *g) {
206 206
 	(void) g;
207 207
 }
208 208
 
209
-static GFXINLINE void set_backlight(GDisplay *g, uint8_t percent) {
209
+static GFXINLINE void set_backlight(GDisplay *g, gU8 percent) {
210 210
 	(void) g;
211 211
 	(void) percent;
212 212
 }

+ 7 - 7
boards/base/STM32F429i-Discovery/chibios/gmouse_lld_STMPE811_board.h

@@ -84,8 +84,8 @@ static GFXINLINE void release_bus(GMouse* m) {
84 84
 
85 85
 }
86 86
 
87
-static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
88
-	uint8_t		txbuf[2];
87
+static void write_reg(GMouse* m, gU8 reg, gU8 val) {
88
+	gU8		txbuf[2];
89 89
 	(void)		m;
90 90
 
91 91
 	txbuf[0] = reg;
@@ -96,8 +96,8 @@ static void write_reg(GMouse* m, uint8_t reg, uint8_t val) {
96 96
 	i2cReleaseBus(&I2CD3);
97 97
 }
98 98
 
99
-static uint8_t read_byte(GMouse* m, uint8_t reg) {
100
-	uint8_t		rxbuf[1];
99
+static gU8 read_byte(GMouse* m, gU8 reg) {
100
+	gU8		rxbuf[1];
101 101
 	(void)		m;
102 102
 
103 103
 	rxbuf[0] = 0;
@@ -109,8 +109,8 @@ static uint8_t read_byte(GMouse* m, uint8_t reg) {
109 109
 	return rxbuf[0];
110 110
 }
111 111
 
112
-static uint16_t read_word(GMouse* m, uint8_t reg) {
113
-	uint8_t		rxbuf[2];
112
+static gU16 read_word(GMouse* m, gU8 reg) {
113
+	gU8		rxbuf[2];
114 114
 	(void)		m;
115 115
 
116 116
 	rxbuf[0] = 0;
@@ -120,7 +120,7 @@ static uint16_t read_word(GMouse* m, uint8_t reg) {
120 120
 	i2cMasterTransmitTimeout(&I2CD3, STMPE811_ADDR, &reg, 1, rxbuf, 2, MS2ST(STMPE811_TIMEOUT));
121 121
 	i2cReleaseBus(&I2CD3);
122 122
 
123
-	return (((uint16_t)rxbuf[0]) << 8) | rxbuf[1];
123
+	return (((gU16)rxbuf[0]) << 8) | rxbuf[1];
124 124
 }
125 125
 
126 126
 #endif /* _GINPUT_LLD_MOUSE_BOARD_H */

+ 8 - 8
boards/base/STM32F429i-Discovery/chibios/stm32f429i_discovery_sdram.c

@@ -182,7 +182,7 @@ void SDRAM_Init(void)
182 182
 void SDRAM_InitSequence(void)
183 183
 {
184 184
   FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
185
-  uint32_t tmpr = 0;
185
+  gU32 tmpr = 0;
186 186
   
187 187
 /* Step 3 --------------------------------------------------------------------*/
188 188
   /* Configure a clock configuration enable command */
@@ -240,7 +240,7 @@ void SDRAM_InitSequence(void)
240 240
   
241 241
 /* Step 7 --------------------------------------------------------------------*/
242 242
   /* Program the external memory mode register */
243
-  tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2          |
243
+  tmpr = (gU32)SDRAM_MODEREG_BURST_LENGTH_2          |
244 244
                    SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |
245 245
                    SDRAM_MODEREG_CAS_LATENCY_3           |
246 246
                    SDRAM_MODEREG_OPERATING_MODE_STANDARD |
@@ -279,9 +279,9 @@ void SDRAM_InitSequence(void)
279 279
   * @param  uwBufferSize: number of words to write. 
280 280
   * @retval None.
281 281
   */
282
-void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize)
282
+void SDRAM_WriteBuffer(gU32* pBuffer, gU32 uwWriteAddress, gU32 uwBufferSize)
283 283
 {
284
-  __IO uint32_t write_pointer = (uint32_t)uwWriteAddress;
284
+  __IO gU32 write_pointer = (gU32)uwWriteAddress;
285 285
 
286 286
   /* Disable write protection */
287 287
   FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE);
@@ -295,7 +295,7 @@ void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBu
295 295
   for (; uwBufferSize != 0; uwBufferSize--) 
296 296
   {
297 297
     /* Transfer data to the memory */
298
-    *(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;
298
+    *(gU32 *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;
299 299
 
300 300
     /* Increment the address*/
301 301
     write_pointer += 4;
@@ -311,9 +311,9 @@ void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBu
311 311
   * @param  uwBufferSize: number of words to write. 
312 312
   * @retval None.
313 313
   */
314
-void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize)
314
+void SDRAM_ReadBuffer(gU32* pBuffer, gU32 uwReadAddress, gU32 uwBufferSize)
315 315
 {
316
-  __IO uint32_t write_pointer = (uint32_t)uwReadAddress;
316
+  __IO gU32 write_pointer = (gU32)uwReadAddress;
317 317
   
318 318
    
319 319
   /* Wait until the SDRAM controller is ready */ 
@@ -324,7 +324,7 @@ void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBuff
324 324
   /* Read data */
325 325
   for(; uwBufferSize != 0x00; uwBufferSize--)
326 326
   {
327
-   *pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer );
327
+   *pBuffer++ = *(__IO gU32 *)(SDRAM_BANK_ADDR + write_pointer );
328 328
     
329 329
    /* Increment the address*/
330 330
     write_pointer += 4;

+ 14 - 14
boards/base/STM32F429i-Discovery/chibios/stm32f429i_discovery_sdram.h

@@ -43,7 +43,7 @@
43 43
 /**
44 44
   * @brief  FMC SDRAM Bank address
45 45
   */   
46
-#define SDRAM_BANK_ADDR     ((uint32_t)0xD0000000)
46
+#define SDRAM_BANK_ADDR     ((gU32)0xD0000000)
47 47
   
48 48
 /**
49 49
   * @brief  FMC SDRAM Memory Width
@@ -72,22 +72,22 @@
72 72
 /**
73 73
   * @brief  FMC SDRAM Mode definition register defines
74 74
   */
75
-#define SDRAM_MODEREG_BURST_LENGTH_1             ((uint16_t)0x0000)
76
-#define SDRAM_MODEREG_BURST_LENGTH_2             ((uint16_t)0x0001)
77
-#define SDRAM_MODEREG_BURST_LENGTH_4             ((uint16_t)0x0002)
78
-#define SDRAM_MODEREG_BURST_LENGTH_8             ((uint16_t)0x0004)
79
-#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((uint16_t)0x0000)
80
-#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((uint16_t)0x0008)
81
-#define SDRAM_MODEREG_CAS_LATENCY_2              ((uint16_t)0x0020)
82
-#define SDRAM_MODEREG_CAS_LATENCY_3              ((uint16_t)0x0030)
83
-#define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((uint16_t)0x0000)
84
-#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) 
85
-#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((uint16_t)0x0200)      
75
+#define SDRAM_MODEREG_BURST_LENGTH_1             ((gU16)0x0000)
76
+#define SDRAM_MODEREG_BURST_LENGTH_2             ((gU16)0x0001)
77
+#define SDRAM_MODEREG_BURST_LENGTH_4             ((gU16)0x0002)
78
+#define SDRAM_MODEREG_BURST_LENGTH_8             ((gU16)0x0004)
79
+#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL      ((gU16)0x0000)
80
+#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED     ((gU16)0x0008)
81
+#define SDRAM_MODEREG_CAS_LATENCY_2              ((gU16)0x0020)
82
+#define SDRAM_MODEREG_CAS_LATENCY_3              ((gU16)0x0030)
83
+#define SDRAM_MODEREG_OPERATING_MODE_STANDARD    ((gU16)0x0000)
84
+#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((gU16)0x0000) 
85
+#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE     ((gU16)0x0200)      
86 86
 
87 87
 void  SDRAM_Init(void);
88 88
 void  SDRAM_InitSequence(void);
89
-void  SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize);
90
-void  SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize);
89
+void  SDRAM_WriteBuffer(gU32* pBuffer, gU32 uwWriteAddress, gU32 uwBufferSize);
90
+void  SDRAM_ReadBuffer(gU32* pBuffer, gU32 uwReadAddress, gU32 uwBufferSize);
91 91
 
92 92
 #ifdef __cplusplus
93 93
 }

+ 68 - 68
boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.c

@@ -57,24 +57,24 @@
57 57
 
58 58
 /* --------------------- FMC registers bit mask ---------------------------- */
59 59
 /* FMC BCRx Mask */
60
-#define BCR_MBKEN_SET              ((uint32_t)0x00000001)
61
-#define BCR_MBKEN_RESET            ((uint32_t)0x000FFFFE)
62
-#define BCR_FACCEN_SET             ((uint32_t)0x00000040)
60
+#define BCR_MBKEN_SET              ((gU32)0x00000001)
61
+#define BCR_MBKEN_RESET            ((gU32)0x000FFFFE)
62
+#define BCR_FACCEN_SET             ((gU32)0x00000040)
63 63
 
64 64
 /* FMC PCRx Mask */
65
-#define PCR_PBKEN_SET              ((uint32_t)0x00000004)
66
-#define PCR_PBKEN_RESET            ((uint32_t)0x000FFFFB)
67
-#define PCR_ECCEN_SET              ((uint32_t)0x00000040)
68
-#define PCR_ECCEN_RESET            ((uint32_t)0x000FFFBF)
69
-#define PCR_MEMORYTYPE_NAND        ((uint32_t)0x00000008)
65
+#define PCR_PBKEN_SET              ((gU32)0x00000004)
66
+#define PCR_PBKEN_RESET            ((gU32)0x000FFFFB)
67
+#define PCR_ECCEN_SET              ((gU32)0x00000040)
68
+#define PCR_ECCEN_RESET            ((gU32)0x000FFFBF)
69
+#define PCR_MEMORYTYPE_NAND        ((gU32)0x00000008)
70 70
 
71 71
 /* FMC SDCRx write protection Mask*/
72
-#define SDCR_WriteProtection_RESET ((uint32_t)0x00007DFF)
72
+#define SDCR_WriteProtection_RESET ((gU32)0x00007DFF)
73 73
 
74 74
 /* FMC SDCMR Mask*/
75
-#define SDCMR_CTB1_RESET           ((uint32_t)0x003FFFEF)
76
-#define SDCMR_CTB2_RESET           ((uint32_t)0x003FFFF7)
77
-#define SDCMR_CTB1_2_RESET         ((uint32_t)0x003FFFE7)
75
+#define SDCMR_CTB1_RESET           ((gU32)0x003FFFEF)
76
+#define SDCMR_CTB2_RESET           ((gU32)0x003FFFF7)
77
+#define SDCMR_CTB1_2_RESET         ((gU32)0x003FFFE7)
78 78
 
79 79
 /* Private macro -------------------------------------------------------------*/
80 80
 /* Private variables ---------------------------------------------------------*/
@@ -134,7 +134,7 @@
134 134
   *            @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4
135 135
   * @retval None
136 136
   */
137
-void FMC_NORSRAMDeInit(uint32_t FMC_Bank)
137
+void FMC_NORSRAMDeInit(gU32 FMC_Bank)
138 138
 {
139 139
   /* Check the parameter */
140 140
   assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
@@ -163,7 +163,7 @@ void FMC_NORSRAMDeInit(uint32_t FMC_Bank)
163 163
   */
164 164
 void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
165 165
 {
166
-  uint32_t tmpr = 0;
166
+  gU32 tmpr = 0;
167 167
 
168 168
   /* Check the parameters */
169 169
   assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank));
@@ -190,7 +190,7 @@ void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
190 190
 
191 191
   /* NOR/SRAM Bank control register configuration */
192 192
   FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] =
193
-            (uint32_t)FMC_NORSRAMInitStruct->FMC_DataAddressMux |
193
+            (gU32)FMC_NORSRAMInitStruct->FMC_DataAddressMux |
194 194
             FMC_NORSRAMInitStruct->FMC_MemoryType |
195 195
             FMC_NORSRAMInitStruct->FMC_MemoryDataWidth |
196 196
             FMC_NORSRAMInitStruct->FMC_BurstAccessMode |
@@ -207,22 +207,22 @@ void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
207 207
 
208 208
   if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR)
209 209
   {
210
-    FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
210
+    FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (gU32)BCR_FACCEN_SET;
211 211
   }
212 212
 
213 213
   /* Configure Continuous clock feature when bank2..4 is used */
214 214
   if((FMC_NORSRAMInitStruct->FMC_ContinousClock == FMC_CClock_SyncAsync) && (FMC_NORSRAMInitStruct->FMC_Bank != FMC_Bank1_NORSRAM1))
215 215
   {
216
-    tmpr = (uint32_t)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((uint32_t)0x0F) << 20));
216
+    tmpr = (gU32)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((gU32)0x0F) << 20));
217 217
 
218 218
     FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1]  |= FMC_NORSRAMInitStruct->FMC_ContinousClock;
219 219
     FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1]  |= FMC_BurstAccessMode_Enable;
220
-    FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (uint32_t)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20));
220
+    FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (gU32)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20));
221 221
   }
222 222
 
223 223
   /* NOR/SRAM Bank timing register configuration */
224 224
   FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] =
225
-            (uint32_t)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime |
225
+            (gU32)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime |
226 226
             (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) |
227 227
             (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) |
228 228
             (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) |
@@ -241,7 +241,7 @@ void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
241 241
     assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode));
242 242
 
243 243
     FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] =
244
-               (uint32_t)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime |
244
+               (gU32)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime |
245 245
                (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4 )|
246 246
                (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) |
247 247
                ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision) << 20) |
@@ -306,7 +306,7 @@ void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
306 306
   * @param  NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
307 307
   * @retval None
308 308
   */
309
-void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState)
309
+void FMC_NORSRAMCmd(gU32 FMC_Bank, FunctionalState NewState)
310 310
 {
311 311
   assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
312 312
   assert_param(IS_FUNCTIONAL_STATE(NewState));
@@ -379,7 +379,7 @@ void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState)
379 379
   *            @arg FMC_Bank3_NAND: FMC Bank3 NAND
380 380
   * @retval None
381 381
   */
382
-void FMC_NANDDeInit(uint32_t FMC_Bank)
382
+void FMC_NANDDeInit(gU32 FMC_Bank)
383 383
 {
384 384
   /* Check the parameter */
385 385
   assert_param(IS_FMC_NAND_BANK(FMC_Bank));
@@ -412,7 +412,7 @@ void FMC_NANDDeInit(uint32_t FMC_Bank)
412 412
   */
413 413
 void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
414 414
 {
415
-  uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
415
+  gU32 tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
416 416
 
417 417
   /* Check the parameters */
418 418
   assert_param(IS_FMC_NAND_BANK(FMC_NANDInitStruct->FMC_Bank));
@@ -432,7 +432,7 @@ void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
432 432
   assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime));
433 433
 
434 434
   /* Set the tmppcr value according to FMC_NANDInitStruct parameters */
435
-  tmppcr = (uint32_t)FMC_NANDInitStruct->FMC_Waitfeature |
435
+  tmppcr = (gU32)FMC_NANDInitStruct->FMC_Waitfeature |
436 436
             PCR_MEMORYTYPE_NAND |
437 437
             FMC_NANDInitStruct->FMC_MemoryDataWidth |
438 438
             FMC_NANDInitStruct->FMC_ECC |
@@ -441,13 +441,13 @@ void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
441 441
             (FMC_NANDInitStruct->FMC_TARSetupTime << 13);
442 442
 
443 443
   /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */
444
-  tmppmem = (uint32_t)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
444
+  tmppmem = (gU32)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
445 445
             (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
446 446
             (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
447 447
             (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
448 448
 
449 449
   /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */
450
-  tmppatt = (uint32_t)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
450
+  tmppatt = (gU32)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
451 451
             (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
452 452
             (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
453 453
             (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
@@ -504,7 +504,7 @@ void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
504 504
   * @param  NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
505 505
   * @retval None
506 506
   */
507
-void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState)
507
+void FMC_NANDCmd(gU32 FMC_Bank, FunctionalState NewState)
508 508
 {
509 509
   assert_param(IS_FMC_NAND_BANK(FMC_Bank));
510 510
   assert_param(IS_FUNCTIONAL_STATE(NewState));
@@ -544,7 +544,7 @@ void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState)
544 544
   *          This parameter can be: ENABLE or DISABLE.
545 545
   * @retval None
546 546
   */
547
-void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState)
547
+void FMC_NANDECCCmd(gU32 FMC_Bank, FunctionalState NewState)
548 548
 {
549 549
   assert_param(IS_FMC_NAND_BANK(FMC_Bank));
550 550
   assert_param(IS_FUNCTIONAL_STATE(NewState));
@@ -583,9 +583,9 @@ void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState)
583 583
   *            @arg FMC_Bank3_NAND: FMC Bank3 NAND
584 584
   * @retval The Error Correction Code (ECC) value.
585 585
   */
586
-uint32_t FMC_GetECC(uint32_t FMC_Bank)
586
+gU32 FMC_GetECC(gU32 FMC_Bank)
587 587
 {
588
-  uint32_t eccval = 0x00000000;
588
+  gU32 eccval = 0x00000000;
589 589
 
590 590
   if(FMC_Bank == FMC_Bank2_NAND)
591 591
   {
@@ -686,25 +686,25 @@ void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
686 686
   assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime));
687 687
 
688 688
   /* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */
689
-  FMC_Bank4->PCR4 = (uint32_t)FMC_PCCARDInitStruct->FMC_Waitfeature |
689
+  FMC_Bank4->PCR4 = (gU32)FMC_PCCARDInitStruct->FMC_Waitfeature |
690 690
                      FMC_NAND_MemoryDataWidth_16b |
691 691
                      (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) |
692 692
                      (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13);
693 693
 
694 694
   /* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */
695
-  FMC_Bank4->PMEM4 = (uint32_t)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
695
+  FMC_Bank4->PMEM4 = (gU32)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
696 696
                       (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
697 697
                       (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
698 698
                       (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
699 699
 
700 700
   /* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */
701
-  FMC_Bank4->PATT4 = (uint32_t)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
701
+  FMC_Bank4->PATT4 = (gU32)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
702 702
                       (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
703 703
                       (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
704 704
                       (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
705 705
 
706 706
   /* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */
707
-  FMC_Bank4->PIO4 = (uint32_t)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime |
707
+  FMC_Bank4->PIO4 = (gU32)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime |
708 708
                      (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) |
709 709
                      (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)|
710 710
                      (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24);
@@ -814,7 +814,7 @@ void FMC_PCCARDCmd(FunctionalState NewState)
814 814
   *            @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
815 815
   * @retval None
816 816
   */
817
-void FMC_SDRAMDeInit(uint32_t FMC_Bank)
817
+void FMC_SDRAMDeInit(gU32 FMC_Bank)
818 818
 {
819 819
   /* Check the parameter */
820 820
   assert_param(IS_FMC_SDRAM_BANK(FMC_Bank));
@@ -837,10 +837,10 @@ void FMC_SDRAMDeInit(uint32_t FMC_Bank)
837 837
 void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
838 838
 {
839 839
   /* temporary registers */
840
-  uint32_t tmpr1 = 0;
841
-  uint32_t tmpr2 = 0;
842
-  uint32_t tmpr3 = 0;
843
-  uint32_t tmpr4 = 0;
840
+  gU32 tmpr1 = 0;
841
+  gU32 tmpr2 = 0;
842
+  gU32 tmpr3 = 0;
843
+  gU32 tmpr4 = 0;
844 844
 
845 845
   /* Check the parameters */
846 846
 
@@ -866,7 +866,7 @@ void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
866 866
   assert_param(IS_FMC_RCD_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay));
867 867
 
868 868
   /* SDRAM bank control register configuration */
869
-  tmpr1 =   (uint32_t)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber |
869
+  tmpr1 =   (gU32)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber |
870 870
              FMC_SDRAMInitStruct->FMC_RowBitsNumber |
871 871
              FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth |
872 872
              FMC_SDRAMInitStruct->FMC_InternalBankNumber |
@@ -882,7 +882,7 @@ void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
882 882
   }
883 883
   else   /* SDCR2 "don't care" bits configuration */
884 884
   {
885
-    tmpr3 = (uint32_t)FMC_SDRAMInitStruct->FMC_SDClockPeriod |
885
+    tmpr3 = (gU32)FMC_SDRAMInitStruct->FMC_SDClockPeriod |
886 886
              FMC_SDRAMInitStruct->FMC_ReadBurst |
887 887
              FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
888 888
 
@@ -892,7 +892,7 @@ void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
892 892
   /* SDRAM bank timing register configuration */
893 893
   if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
894 894
   {
895
-    tmpr2 =   (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
895
+    tmpr2 =   (gU32)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
896 896
             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
897 897
             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
898 898
             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
@@ -904,12 +904,12 @@ void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
904 904
   }
905 905
   else   /* SDTR "don't care bits configuration */
906 906
   {
907
-    tmpr2 =   (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
907
+    tmpr2 =   (gU32)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
908 908
             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
909 909
             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
910 910
             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16);
911 911
 
912
-    tmpr4 =   (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
912
+    tmpr4 =   (gU32)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
913 913
             (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20);
914 914
 
915 915
             FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4;
@@ -956,7 +956,7 @@ void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
956 956
   */
957 957
 void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct)
958 958
 {
959
-  uint32_t tmpr = 0x0;
959
+  gU32 tmpr = 0x0;
960 960
 
961 961
   /* check parameters */
962 962
   assert_param(IS_FMC_COMMAND_MODE(FMC_SDRAMCommandStruct->FMC_CommandMode));
@@ -964,7 +964,7 @@ void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct)
964 964
   assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber));
965 965
   assert_param(IS_FMC_MODE_REGISTER(FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition));
966 966
 
967
-  tmpr =   (uint32_t)(FMC_SDRAMCommandStruct->FMC_CommandMode |
967
+  tmpr =   (gU32)(FMC_SDRAMCommandStruct->FMC_CommandMode |
968 968
                       FMC_SDRAMCommandStruct->FMC_CommandTarget |
969 969
                      (((FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)-1)<<5) |
970 970
                      ((FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)<<9));
@@ -980,9 +980,9 @@ void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct)
980 980
   *                     FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
981 981
   * @retval The FMC SDRAM bank mode status
982 982
   */
983
-uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank)
983
+gU32 FMC_GetModeStatus(gU32 SDRAM_Bank)
984 984
 {
985
-  uint32_t tmpreg = 0;
985
+  gU32 tmpreg = 0;
986 986
 
987 987
   /* Check the parameter */
988 988
   assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank));
@@ -990,11 +990,11 @@ uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank)
990 990
   /* Get the busy flag status */
991 991
   if(SDRAM_Bank == FMC_Bank1_SDRAM)
992 992
   {
993
-    tmpreg = (uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1);
993
+    tmpreg = (gU32)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1);
994 994
   }
995 995
   else
996 996
   {
997
-    tmpreg = ((uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2);
997
+    tmpreg = ((gU32)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2);
998 998
   }
999 999
 
1000 1000
   /* Return the mode status */
@@ -1006,7 +1006,7 @@ uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank)
1006 1006
   * @param  FMC_Count: specifies the Refresh timer count.
1007 1007
   * @retval None
1008 1008
   */
1009
-void FMC_SetRefreshCount(uint32_t FMC_Count)
1009
+void FMC_SetRefreshCount(gU32 FMC_Count)
1010 1010
 {
1011 1011
   /* check the parameters */
1012 1012
   assert_param(IS_FMC_REFRESH_COUNT(FMC_Count));
@@ -1020,7 +1020,7 @@ void FMC_SetRefreshCount(uint32_t FMC_Count)
1020 1020
   * @param  FMC_Number: specifies the auto Refresh number.
1021 1021
   * @retval None
1022 1022
   */
1023
-void FMC_SetAutoRefresh_Number(uint32_t FMC_Number)
1023
+void FMC_SetAutoRefresh_Number(gU32 FMC_Number)
1024 1024
 {
1025 1025
   /* check the parameters */
1026 1026
   assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_Number));
@@ -1036,7 +1036,7 @@ void FMC_SetAutoRefresh_Number(uint32_t FMC_Number)
1036 1036
   *          This parameter can be: ENABLE or DISABLE.
1037 1037
   * @retval None
1038 1038
   */
1039
-void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState)
1039
+void FMC_SDRAMWriteProtectionConfig(gU32 SDRAM_Bank, FunctionalState NewState)
1040 1040
 {
1041 1041
   /* Check the parameter */
1042 1042
   assert_param(IS_FUNCTIONAL_STATE(NewState));
@@ -1088,7 +1088,7 @@ void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewStat
1088 1088
   *          This parameter can be: ENABLE or DISABLE.
1089 1089
   * @retval None
1090 1090
   */
1091
-void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState)
1091
+void FMC_ITConfig(gU32 FMC_Bank, gU32 FMC_IT, FunctionalState NewState)
1092 1092
 {
1093 1093
   assert_param(IS_FMC_IT_BANK(FMC_Bank));
1094 1094
   assert_param(IS_FMC_IT(FMC_IT));
@@ -1124,23 +1124,23 @@ void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState)
1124 1124
     if(FMC_Bank == FMC_Bank2_NAND)
1125 1125
     {
1126 1126
 
1127
-      FMC_Bank2->SR2 &= (uint32_t)~FMC_IT;
1127
+      FMC_Bank2->SR2 &= (gU32)~FMC_IT;
1128 1128
     }
1129 1129
     /* Disable the selected FMC_Bank3 interrupts */
1130 1130
     else if (FMC_Bank == FMC_Bank3_NAND)
1131 1131
     {
1132
-      FMC_Bank3->SR3 &= (uint32_t)~FMC_IT;
1132
+      FMC_Bank3->SR3 &= (gU32)~FMC_IT;
1133 1133
     }
1134 1134
     /* Disable the selected FMC_Bank4 interrupts */
1135 1135
     else if(FMC_Bank == FMC_Bank4_PCCARD)
1136 1136
     {
1137
-      FMC_Bank4->SR4 &= (uint32_t)~FMC_IT;
1137
+      FMC_Bank4->SR4 &= (gU32)~FMC_IT;
1138 1138
     }
1139 1139
     /* Disable the selected FMC_Bank5_6 interrupt */
1140 1140
     else
1141 1141
     {
1142 1142
       /* Disables the interrupt if the refresh error flag is not set */
1143
-      FMC_Bank5_6->SDRTR &= (uint32_t)~FMC_IT;
1143
+      FMC_Bank5_6->SDRTR &= (gU32)~FMC_IT;
1144 1144
     }
1145 1145
   }
1146 1146
 }
@@ -1165,10 +1165,10 @@ void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState)
1165 1165
   *            @arg FMC_FLAG_Busy: Busy status Flag.
1166 1166
   * @retval The new state of FMC_FLAG (SET or RESET).
1167 1167
   */
1168
-FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG)
1168
+FlagStatus FMC_GetFlagStatus(gU32 FMC_Bank, gU32 FMC_FLAG)
1169 1169
 {
1170 1170
   FlagStatus bitstatus = RESET;
1171
-  uint32_t tmpsr = 0x00000000;
1171
+  gU32 tmpsr = 0x00000000;
1172 1172
 
1173 1173
   /* Check the parameters */
1174 1174
   assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
@@ -1221,7 +1221,7 @@ FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG)
1221 1221
   *            @arg FMC_FLAG_Refresh: Refresh error Flag.
1222 1222
   * @retval None
1223 1223
   */
1224
-void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG)
1224
+void FMC_ClearFlag(gU32 FMC_Bank, gU32 FMC_FLAG)
1225 1225
 {
1226 1226
  /* Check the parameters */
1227 1227
   assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
@@ -1264,13 +1264,13 @@ void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG)
1264 1264
   *            @arg FMC_IT_Refresh: Refresh error detection interrupt.
1265 1265
   * @retval The new state of FMC_IT (SET or RESET).
1266 1266
   */
1267
-ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT)
1267
+ITStatus FMC_GetITStatus(gU32 FMC_Bank, gU32 FMC_IT)
1268 1268
 {
1269 1269
   ITStatus bitstatus = RESET;
1270
-  uint32_t tmpsr = 0x0;
1271
-  uint32_t tmpsr2 = 0x0;
1272
-  uint32_t itstatus = 0x0;
1273
-  uint32_t itenable = 0x0;
1270
+  gU32 tmpsr = 0x0;
1271
+  gU32 tmpsr2 = 0x0;
1272
+  gU32 itstatus = 0x0;
1273
+  gU32 itenable = 0x0;
1274 1274
 
1275 1275
   /* Check the parameters */
1276 1276
   assert_param(IS_FMC_IT_BANK(FMC_Bank));
@@ -1308,7 +1308,7 @@ ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT)
1308 1308
     itstatus = tmpsr & (FMC_IT >> 3);
1309 1309
   }
1310 1310
 
1311
-  if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
1311
+  if ((itstatus != (gU32)RESET)  && (itenable != (gU32)RESET))
1312 1312
   {
1313 1313
     bitstatus = SET;
1314 1314
   }
@@ -1336,7 +1336,7 @@ ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT)
1336 1336
   *            @arg FMC_IT_Refresh: Refresh error detection interrupt.
1337 1337
   * @retval None
1338 1338
   */
1339
-void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT)
1339
+void FMC_ClearITPendingBit(gU32 FMC_Bank, gU32 FMC_IT)
1340 1340
 {
1341 1341
   /* Check the parameters */
1342 1342
   assert_param(IS_FMC_IT_BANK(FMC_Bank));

+ 171 - 171
boards/base/STM32F429i-Discovery/chibios/stm32f4xx_fmc.h